UefiCpuPkg: Add PiSmmCpuDxeSmm module IA32 files
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18646 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
mdkinney
911
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S
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911
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S
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@@ -0,0 +1,911 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmiException.S
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#
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# Abstract:
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#
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# Exception handlers used in SM mode
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(SmiPFHandler)
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ASM_GLOBAL ASM_PFX(PageFaultStubFunction)
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ASM_GLOBAL ASM_PFX(gSmiMtrrs)
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ASM_GLOBAL ASM_PFX(gcSmiIdtr)
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ASM_GLOBAL ASM_PFX(gcSmiGdtr)
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ASM_GLOBAL ASM_PFX(gcPsd)
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ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))
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.data
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NullSeg: .quad 0 # reserved by architecture
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CodeSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x9b
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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ProtModeCodeSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x9b
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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ProtModeSsSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x93
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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DataSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x93
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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CodeSeg16:
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.word -1
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.word 0
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.byte 0
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.byte 0x9b
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.byte 0x8f
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.byte 0
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DataSeg16:
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.word -1
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.word 0
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.byte 0
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.byte 0x93
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.byte 0x8f
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.byte 0
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CodeSeg64:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x9b
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.byte 0xaf # LimitHigh
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.byte 0 # BaseHigh
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.equ GDT_SIZE, .- NullSeg
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TssSeg:
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.word TSS_DESC_SIZE # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x89
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.byte 0x80 # LimitHigh
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.byte 0 # BaseHigh
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ExceptionTssSeg:
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.word TSS_DESC_SIZE # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x89
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.byte 0x80 # LimitHigh
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.byte 0 # BaseHigh
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.equ CODE_SEL, CodeSeg32 - NullSeg
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.equ DATA_SEL, DataSeg32 - NullSeg
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.equ TSS_SEL, TssSeg - NullSeg
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.equ EXCEPTION_TSS_SEL, ExceptionTssSeg - NullSeg
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# IA32 TSS fields
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.equ TSS_ESP0, 4
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.equ TSS_SS0, 8
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.equ TSS_ESP1, 12
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.equ TSS_SS1, 16
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.equ TSS_ESP2, 20
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.equ TSS_SS2, 24
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.equ TSS_CR3, 28
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.equ TSS_EIP, 32
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.equ TSS_EFLAGS, 36
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.equ TSS_EAX, 40
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.equ TSS_ECX, 44
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.equ TSS_EDX, 48
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.equ TSS_EBX, 52
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.equ TSS_ESP, 56
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.equ TSS_EBP, 60
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.equ TSS_ESI, 64
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.equ TSS_EDI, 68
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.equ TSS_ES, 72
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.equ TSS_CS, 76
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.equ TSS_SS, 80
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.equ TSS_DS, 84
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.equ TSS_FS, 88
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.equ TSS_GS, 92
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.equ TSS_LDT, 96
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# Create 2 TSS segments just after GDT
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TssDescriptor:
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.word 0 # PreviousTaskLink
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.word 0 # Reserved
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.long 0 # ESP0
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.word 0 # SS0
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.word 0 # Reserved
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.long 0 # ESP1
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.word 0 # SS1
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.word 0 # Reserved
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.long 0 # ESP2
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.word 0 # SS2
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.word 0 # Reserved
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.long 0 # CR3
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.long 0 # EIP
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.long 0 # EFLAGS
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.long 0 # EAX
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.long 0 # ECX
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.long 0 # EDX
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.long 0 # EBX
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.long 0 # ESP
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.long 0 # EBP
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.long 0 # ESI
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.long 0 # EDI
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.word 0 # ES
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.word 0 # Reserved
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.word 0 # CS
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.word 0 # Reserved
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.word 0 # SS
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.word 0 # Reserved
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.word 0 # DS
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.word 0 # Reserved
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.word 0 # FS
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.word 0 # Reserved
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.word 0 # GS
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.word 0 # Reserved
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.word 0 # LDT Selector
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.word 0 # Reserved
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.word 0 # T
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.word 0 # I/O Map Base
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.equ TSS_DESC_SIZE, . - TssDescriptor
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ExceptionTssDescriptor:
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.word 0 # PreviousTaskLink
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.word 0 # Reserved
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.long 0 # ESP0
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.word 0 # SS0
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.word 0 # Reserved
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.long 0 # ESP1
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.word 0 # SS1
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.word 0 # Reserved
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.long 0 # ESP2
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.word 0 # SS2
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.word 0 # Reserved
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.long 0 # CR3
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.long PFHandlerEntry # EIP
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.long 00000002 # EFLAGS
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.long 0 # EAX
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.long 0 # ECX
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.long 0 # EDX
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.long 0 # EBX
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.long 0 # ESP
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.long 0 # EBP
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.long 0 # ESI
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.long 0 # EDI
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.word DATA_SEL # ES
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.word 0 # Reserved
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.word CODE_SEL # CS
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.word 0 # Reserved
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.word DATA_SEL # SS
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.word 0 # Reserved
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.word DATA_SEL # DS
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.word 0 # Reserved
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.word DATA_SEL # FS
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.word 0 # Reserved
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.word DATA_SEL # GS
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.word 0 # Reserved
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.word 0 # LDT Selector
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.word 0 # Reserved
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.word 0 # T
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.word 0 # I/O Map Base
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ASM_PFX(gcPsd):
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.ascii "PSDSIG "
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.word PSD_SIZE
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.word 2
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.word 1 << 2
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.word CODE_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word 0
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.long 0
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.long 0
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.long 0
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.long 0
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.quad 0
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.long NullSeg
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.long 0
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.long GDT_SIZE
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.long 0
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.space 24, 0
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.long ASM_PFX(gSmiMtrrs)
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.long 0
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.equ PSD_SIZE, . - ASM_PFX(gcPsd)
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ASM_PFX(gcSmiGdtr): .word GDT_SIZE - 1
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.long NullSeg
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ASM_PFX(gcSmiIdtr): .word IDT_SIZE - 1
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.long _SmiIDT
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_SmiIDT:
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# The following segment repeats 32 times:
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# No. 1
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 2
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 3
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 4
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 5
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 6
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 7
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 8
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 9
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 10
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 11
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 12
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 13
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 14
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 15
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 16
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 17
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 18
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 19
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 20
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 21
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 22
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 23
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 24
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 25
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 26
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 27
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 28
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 29
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 30
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 31
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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# No. 32
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.equ IDT_SIZE, . - _SmiIDT
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TaskGateDescriptor:
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.word 0 # Reserved
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.word EXCEPTION_TSS_SEL # TSS Segment selector
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.byte 0 # Reserved
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||||
.byte 0x85 # Task Gate, present, DPL = 0
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||||
.word 0 # Reserved
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||||
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.text
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#------------------------------------------------------------------------------
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# PageFaultIdtHandlerSmmProfile is the entry point for all exceptions
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#
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# Stack:
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#+---------------------+
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||||
#+ EFlags +
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#+---------------------+
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||||
#+ CS +
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#+---------------------+
|
||||
#+ EIP +
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#+---------------------+
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||||
#+ Error Code +
|
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#+---------------------+
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||||
#+ Vector Number +
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#+---------------------+
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#+ EBP +
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#+---------------------+ <-- EBP
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#
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# RSP set to odd multiple of 8 means ErrCode PRESENT
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(PageFaultIdtHandlerSmmProfile)
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ASM_PFX(PageFaultIdtHandlerSmmProfile):
|
||||
pushl $0x0e # Page Fault
|
||||
pushl %ebp
|
||||
movl %esp, %ebp
|
||||
|
||||
|
||||
#
|
||||
# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
|
||||
# is 16-byte aligned
|
||||
#
|
||||
andl $0xfffffff0, %esp
|
||||
subl $12, %esp
|
||||
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||||
## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
pushl %eax
|
||||
pushl %ecx
|
||||
pushl %edx
|
||||
pushl %ebx
|
||||
leal (6*4)(%ebp), %ecx
|
||||
pushl %ecx # ESP
|
||||
pushl (%ebp) # EBP
|
||||
pushl %esi
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||||
pushl %edi
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||||
|
||||
## UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
movl %ss, %eax
|
||||
pushl %eax
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||||
movzwl (4*4)(%ebp), %eax
|
||||
pushl %eax
|
||||
movl %ds, %eax
|
||||
pushl %eax
|
||||
movl %es, %eax
|
||||
pushl %eax
|
||||
movl %fs, %eax
|
||||
pushl %eax
|
||||
movl %gs, %eax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 Eip;
|
||||
movl (3*4)(%ebp), %eax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 Gdtr[2], Idtr[2];
|
||||
subl $8, %esp
|
||||
sidt (%esp)
|
||||
movl 2(%esp), %eax
|
||||
xchgl (%esp), %eax
|
||||
andl $0xffff, %eax
|
||||
movl %eax, 4(%esp)
|
||||
|
||||
subl $8, %esp
|
||||
sgdt (%esp)
|
||||
movl 2(%esp), %eax
|
||||
xchgl (%esp), %eax
|
||||
andl $0xffff, %eax
|
||||
movl %eax, 4(%esp)
|
||||
|
||||
## UINT32 Ldtr, Tr;
|
||||
xorl %eax, %eax
|
||||
strw %ax
|
||||
pushl %eax
|
||||
sldtw %ax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 EFlags;
|
||||
movl (5*4)(%ebp), %eax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
movl %cr4, %eax
|
||||
orl $0x208, %eax
|
||||
movl %eax, %cr4
|
||||
pushl %eax
|
||||
movl %cr3, %eax
|
||||
pushl %eax
|
||||
movl %cr2, %eax
|
||||
pushl %eax
|
||||
xorl %eax, %eax
|
||||
pushl %eax
|
||||
movl %cr0, %eax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
movl %dr7, %eax
|
||||
pushl %eax
|
||||
movl %dr6, %eax
|
||||
pushl %eax
|
||||
movl %dr3, %eax
|
||||
pushl %eax
|
||||
movl %dr2, %eax
|
||||
pushl %eax
|
||||
movl %dr1, %eax
|
||||
pushl %eax
|
||||
movl %dr0, %eax
|
||||
pushl %eax
|
||||
|
||||
## FX_SAVE_STATE_IA32 FxSaveState;
|
||||
subl $512, %esp
|
||||
movl %esp, %edi
|
||||
.byte 0x0f, 0xae, 0x07 #fxsave [edi]
|
||||
|
||||
# UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
|
||||
cld
|
||||
|
||||
## UINT32 ExceptionData;
|
||||
pushl (2*4)(%ebp)
|
||||
|
||||
## call into exception handler
|
||||
|
||||
## Prepare parameter and call
|
||||
movl %esp, %edx
|
||||
pushl %edx
|
||||
movl (1*4)(%ebp), %edx
|
||||
pushl %edx
|
||||
|
||||
#
|
||||
# Call External Exception Handler
|
||||
#
|
||||
movl $ASM_PFX(SmiPFHandler), %eax
|
||||
call *%eax
|
||||
addl $8, %esp
|
||||
jmp L4
|
||||
|
||||
L4:
|
||||
## UINT32 ExceptionData;
|
||||
addl $4, %esp
|
||||
|
||||
## FX_SAVE_STATE_IA32 FxSaveState;
|
||||
movl %esp, %esi
|
||||
.byte 0xf, 0xae, 0xe # fxrstor [esi]
|
||||
addl $512, %esp
|
||||
|
||||
## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
## Skip restoration of DRx registers to support debuggers
|
||||
## that set breakpoints in interrupt/exception context
|
||||
addl $4*6, %esp
|
||||
|
||||
## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
popl %eax
|
||||
movl %eax, %cr0
|
||||
addl $4, %esp # not for Cr1
|
||||
popl %eax
|
||||
movl %eax, %cr2
|
||||
popl %eax
|
||||
movl %eax, %cr3
|
||||
popl %eax
|
||||
movl %eax, %cr4
|
||||
|
||||
## UINT32 EFlags;
|
||||
popl (5*4)(%ebp)
|
||||
|
||||
## UINT32 Ldtr, Tr;
|
||||
## UINT32 Gdtr[2], Idtr[2];
|
||||
## Best not let anyone mess with these particular registers...
|
||||
addl $24, %esp
|
||||
|
||||
## UINT32 Eip;
|
||||
popl (3*4)(%ebp)
|
||||
|
||||
## UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
## NOTE - modified segment registers could hang the debugger... We
|
||||
## could attempt to insulate ourselves against this possibility,
|
||||
## but that poses risks as well.
|
||||
##
|
||||
popl %gs
|
||||
popl %fs
|
||||
popl %es
|
||||
popl %ds
|
||||
popl (4*4)(%ebp)
|
||||
popl %ss
|
||||
|
||||
## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
popl %edi
|
||||
popl %esi
|
||||
addl $4, %esp # not for ebp
|
||||
addl $4, %esp # not for esp
|
||||
popl %ebx
|
||||
popl %edx
|
||||
popl %ecx
|
||||
popl %eax
|
||||
|
||||
movl %ebp, %esp
|
||||
popl %ebp
|
||||
|
||||
# Enable TF bit after page fault handler runs
|
||||
btsl $8, 16(%esp) # EFLAGS
|
||||
|
||||
addl $8, %esp # skip INT# & ErrCode
|
||||
Return:
|
||||
iret
|
||||
#
|
||||
# Page Fault Exception Handler entry when SMM Stack Guard is enabled
|
||||
# Executiot starts here after a task switch
|
||||
#
|
||||
PFHandlerEntry:
|
||||
#
|
||||
# Get this processor's TSS
|
||||
#
|
||||
subl $8, %esp
|
||||
sgdt 2(%esp)
|
||||
movl 4(%esp), %eax # GDT base
|
||||
addl $8, %esp
|
||||
movl (TSS_SEL+2)(%eax), %ecx
|
||||
shll $8, %ecx
|
||||
movb (TSS_SEL+7)(%eax), %cl
|
||||
rorl $8, %ecx # ecx = TSS base
|
||||
|
||||
movl %esp, %ebp
|
||||
|
||||
#
|
||||
# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
|
||||
# is 16-byte aligned
|
||||
#
|
||||
andl $0xfffffff0, %esp
|
||||
subl $12, %esp
|
||||
|
||||
## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
pushl TSS_EAX(%ecx)
|
||||
pushl TSS_ECX(%ecx)
|
||||
pushl TSS_EDX(%ecx)
|
||||
pushl TSS_EBX(%ecx)
|
||||
pushl TSS_ESP(%ecx)
|
||||
pushl TSS_EBP(%ecx)
|
||||
pushl TSS_ESI(%ecx)
|
||||
pushl TSS_EDI(%ecx)
|
||||
|
||||
## UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
movzwl TSS_SS(%ecx), %eax
|
||||
pushl %eax
|
||||
movzwl TSS_CS(%ecx), %eax
|
||||
pushl %eax
|
||||
movzwl TSS_DS(%ecx), %eax
|
||||
pushl %eax
|
||||
movzwl TSS_ES(%ecx), %eax
|
||||
pushl %eax
|
||||
movzwl TSS_FS(%ecx), %eax
|
||||
pushl %eax
|
||||
movzwl TSS_GS(%ecx), %eax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 Eip;
|
||||
pushl TSS_EIP(%ecx)
|
||||
|
||||
## UINT32 Gdtr[2], Idtr[2];
|
||||
subl $8, %esp
|
||||
sidt (%esp)
|
||||
movl 2(%esp), %eax
|
||||
xchgl (%esp), %eax
|
||||
andl $0xFFFF, %eax
|
||||
movl %eax, 4(%esp)
|
||||
|
||||
subl $8, %esp
|
||||
sgdt (%esp)
|
||||
movl 2(%esp), %eax
|
||||
xchgl (%esp), %eax
|
||||
andl $0xFFFF, %eax
|
||||
movl %eax, 4(%esp)
|
||||
|
||||
## UINT32 Ldtr, Tr;
|
||||
movl $TSS_SEL, %eax
|
||||
pushl %eax
|
||||
movzwl TSS_LDT(%ecx), %eax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 EFlags;
|
||||
pushl TSS_EFLAGS(%ecx)
|
||||
|
||||
## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
movl %cr4, %eax
|
||||
orl $0x208, %eax
|
||||
movl %eax, %cr4
|
||||
pushl %eax
|
||||
movl %cr3, %eax
|
||||
pushl %eax
|
||||
movl %cr2, %eax
|
||||
pushl %eax
|
||||
xorl %eax, %eax
|
||||
pushl %eax
|
||||
movl %cr0, %eax
|
||||
pushl %eax
|
||||
|
||||
## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
movl %dr7, %eax
|
||||
pushl %eax
|
||||
movl %dr6, %eax
|
||||
pushl %eax
|
||||
movl %dr3, %eax
|
||||
pushl %eax
|
||||
movl %dr2, %eax
|
||||
pushl %eax
|
||||
movl %dr1, %eax
|
||||
pushl %eax
|
||||
movl %dr0, %eax
|
||||
pushl %eax
|
||||
|
||||
## FX_SAVE_STATE_IA32 FxSaveState;
|
||||
## Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
|
||||
## when executing fxsave/fxrstor instruction
|
||||
clts
|
||||
subl $512, %esp
|
||||
movl %esp, %edi
|
||||
.byte 0x0f, 0xae, 0x07 #fxsave [edi]
|
||||
|
||||
# UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
|
||||
cld
|
||||
|
||||
## UINT32 ExceptionData;
|
||||
pushl (%ebp)
|
||||
|
||||
## call into exception handler
|
||||
movl %ecx, %ebx
|
||||
movl $ASM_PFX(SmiPFHandler), %eax
|
||||
|
||||
## Prepare parameter and call
|
||||
movl %esp, %edx
|
||||
pushl %edx
|
||||
movl $14, %edx
|
||||
pushl %edx
|
||||
|
||||
#
|
||||
# Call External Exception Handler
|
||||
#
|
||||
call *%eax
|
||||
addl $8, %esp
|
||||
|
||||
movl %ebx, %ecx
|
||||
## UINT32 ExceptionData;
|
||||
addl $4, %esp
|
||||
|
||||
## FX_SAVE_STATE_IA32 FxSaveState;
|
||||
movl %esp, %esi
|
||||
.byte 0xf, 0xae, 0xe # fxrstor [esi]
|
||||
addl $512, %esp
|
||||
|
||||
## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
## Skip restoration of DRx registers to support debuggers
|
||||
## that set breakpoints in interrupt/exception context
|
||||
addl $4*6, %esp
|
||||
|
||||
## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
popl %eax
|
||||
movl %eax, %cr0
|
||||
addl $4, %esp # not for Cr1
|
||||
popl %eax
|
||||
movl %eax, %cr2
|
||||
popl %eax
|
||||
movl %eax, TSS_CR3(%ecx)
|
||||
popl %eax
|
||||
movl %eax, %cr4
|
||||
|
||||
## UINT32 EFlags;
|
||||
popl TSS_EFLAGS(%ecx)
|
||||
|
||||
## UINT32 Ldtr, Tr;
|
||||
## UINT32 Gdtr[2], Idtr[2];
|
||||
## Best not let anyone mess with these particular registers...
|
||||
addl $24, %esp
|
||||
|
||||
## UINT32 Eip;
|
||||
popl TSS_EIP(%ecx)
|
||||
|
||||
## UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
## NOTE - modified segment registers could hang the debugger... We
|
||||
## could attempt to insulate ourselves against this possibility,
|
||||
## but that poses risks as well.
|
||||
##
|
||||
popl %eax
|
||||
movw %ax, TSS_GS(%ecx)
|
||||
popl %eax
|
||||
movw %ax, TSS_FS(%ecx)
|
||||
popl %eax
|
||||
movw %ax, TSS_ES(%ecx)
|
||||
popl %eax
|
||||
movw %ax, TSS_DS(%ecx)
|
||||
popl %eax
|
||||
movw %ax, TSS_CS(%ecx)
|
||||
popl %eax
|
||||
movw %ax, TSS_SS(%ecx)
|
||||
|
||||
## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
popl TSS_EDI(%ecx)
|
||||
popl TSS_ESI(%ecx)
|
||||
addl $4, %esp # not for ebp
|
||||
addl $4, %esp # not for esp
|
||||
popl TSS_EBX(%ecx)
|
||||
popl TSS_EDX(%ecx)
|
||||
popl TSS_ECX(%ecx)
|
||||
popl TSS_EAX(%ecx)
|
||||
|
||||
movl %ebp, %esp
|
||||
|
||||
# Set single step DB# if SMM profile is enabled and page fault exception happens
|
||||
cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))
|
||||
jz Done2
|
||||
# Create return context for iret in stub function
|
||||
movl TSS_ESP(%ecx), %eax # Get old stack pointer
|
||||
movl TSS_EIP(%ecx), %ebx
|
||||
movl %ebx, -0xc(%eax) # create EIP in old stack
|
||||
movzwl TSS_CS(%ecx), %ebx
|
||||
movl %ebx, -0x8(%eax) # create CS in old stack
|
||||
movl TSS_EFLAGS(%ecx), %ebx
|
||||
btsl $8,%ebx
|
||||
movl %ebx, -0x4(%eax) # create eflags in old stack
|
||||
movl TSS_ESP(%ecx), %eax # Get old stack pointer
|
||||
subl $12, %eax # minus 12 byte
|
||||
movl %eax, TSS_ESP(%ecx) # Set new stack pointer
|
||||
|
||||
# Replace the EIP of interrupted task with stub function
|
||||
movl $ASM_PFX(PageFaultStubFunction), %eax
|
||||
movl %eax, TSS_EIP(%ecx)
|
||||
# Jump to the iret so next page fault handler as a task will start again after iret.
|
||||
|
||||
Done2:
|
||||
|
||||
addl $4, %esp # skip ErrCode
|
||||
|
||||
jmp Return
|
||||
|
||||
ASM_PFX(PageFaultStubFunction):
|
||||
#
|
||||
# we need clean TS bit in CR0 to execute
|
||||
# x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
|
||||
#
|
||||
clts
|
||||
iret
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InitializeIDTSmmStackGuard)
|
||||
ASM_PFX(InitializeIDTSmmStackGuard):
|
||||
pushl %ebx
|
||||
#
|
||||
# If SMM Stack Guard feature is enabled, the Page Fault Exception entry in IDT
|
||||
# is a Task Gate Descriptor so that when a Page Fault Exception occurs,
|
||||
# the processors can use a known good stack in case stack ran out.
|
||||
#
|
||||
leal _SmiIDT + 14 * 8, %ebx
|
||||
leal TaskGateDescriptor, %edx
|
||||
movl (%edx), %eax
|
||||
movl %eax, (%ebx)
|
||||
movl 4(%edx), %eax
|
||||
movl %eax, 4(%ebx)
|
||||
|
||||
popl %ebx
|
||||
ret
|
||||
Reference in New Issue
Block a user