SecurityPkg: Add TPM PTP support in TPM2 device lib.
TPM2 hardware may support PTP FIFO/TIS interface or PTP CRB interface. The original lib only handles PTP FIFO/TIS interface. This patch adds PTP CRB interface support. The current logic is that lib will runtime detect TPM device interface (CRB or FIFO/TIS) and call proper function to access hardware. It is compatible for old TPM2 FIFO/TIS device and new TPM2 CRB device. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19740 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -1,7 +1,7 @@
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/** @file
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TIS (TPM Interface Specification) functions used by dTPM2.0 library.
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Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@@ -23,168 +23,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include <Library/Tpm2DeviceLib.h>
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#include <Library/PcdLib.h>
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//
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// Set structure alignment to 1-byte
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//
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#pragma pack (1)
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//
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// Register set map as specified in TIS specification Chapter 10
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//
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typedef struct {
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///
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/// Used to gain ownership for this particular port.
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///
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UINT8 Access; // 0
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UINT8 Reserved1[7]; // 1
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///
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/// Controls interrupts.
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///
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UINT32 IntEnable; // 8
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///
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/// SIRQ vector to be used by the TPM.
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///
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UINT8 IntVector; // 0ch
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UINT8 Reserved2[3]; // 0dh
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///
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/// What caused interrupt.
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///
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UINT32 IntSts; // 10h
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///
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/// Shows which interrupts are supported by that particular TPM.
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///
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UINT32 IntfCapability; // 14h
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///
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/// Status Register. Provides status of the TPM.
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///
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UINT8 Status; // 18h
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///
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/// Number of consecutive writes that can be done to the TPM.
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///
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UINT16 BurstCount; // 19h
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///
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/// TPM2 support CANCEL at BIT[24] of STATUS register (WO)
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///
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UINT8 StatusEx; // 1Bh
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UINT8 Reserved3[8];
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///
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/// Read or write FIFO, depending on transaction.
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///
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UINT32 DataFifo; // 24h
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UINT8 Reserved4[0xed8]; // 28h
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///
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/// Vendor ID
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///
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UINT16 Vid; // 0f00h
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///
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/// Device ID
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///
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UINT16 Did; // 0f02h
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///
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/// Revision ID
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///
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UINT8 Rid; // 0f04h
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///
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/// TCG defined configuration registers.
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///
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UINT8 TcgDefined[0x7b]; // 0f05h
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///
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/// Alias to I/O legacy space.
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///
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UINT32 LegacyAddress1; // 0f80h
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///
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/// Additional 8 bits for I/O legacy space extension.
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///
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UINT32 LegacyAddress1Ex; // 0f84h
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///
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/// Alias to second I/O legacy space.
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///
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UINT32 LegacyAddress2; // 0f88h
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///
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/// Additional 8 bits for second I/O legacy space extension.
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///
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UINT32 LegacyAddress2Ex; // 0f8ch
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///
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/// Vendor-defined configuration registers.
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///
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UINT8 VendorDefined[0x70];// 0f90h
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} TIS_PC_REGISTERS;
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//
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// Restore original structure alignment
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//
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#pragma pack ()
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//
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// Define pointer types used to access TIS registers on PC
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//
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typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
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//
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// Define bits of ACCESS and STATUS registers
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//
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///
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/// This bit is a 1 to indicate that the other bits in this register are valid.
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///
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#define TIS_PC_VALID BIT7
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///
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/// Indicate that this locality is active.
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///
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#define TIS_PC_ACC_ACTIVE BIT5
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///
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/// Set to 1 to indicate that this locality had the TPM taken away while
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/// this locality had the TIS_PC_ACC_ACTIVE bit set.
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///
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#define TIS_PC_ACC_SEIZED BIT4
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///
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/// Set to 1 to indicate that TPM MUST reset the
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/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
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/// locality that is writing this bit.
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///
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#define TIS_PC_ACC_SEIZE BIT3
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///
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/// When this bit is 1, another locality is requesting usage of the TPM.
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///
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#define TIS_PC_ACC_PENDIND BIT2
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///
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/// Set to 1 to indicate that this locality is requesting to use TPM.
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///
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#define TIS_PC_ACC_RQUUSE BIT1
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///
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/// A value of 1 indicates that a T/OS has not been established on the platform
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///
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#define TIS_PC_ACC_ESTABLISH BIT0
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///
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/// When this bit is 1, TPM is in the Ready state,
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/// indicating it is ready to receive a new command.
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///
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#define TIS_PC_STS_READY BIT6
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///
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/// Write a 1 to this bit to cause the TPM to execute that command.
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///
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#define TIS_PC_STS_GO BIT5
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///
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/// This bit indicates that the TPM has data available as a response.
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///
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#define TIS_PC_STS_DATA BIT4
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///
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/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
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///
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#define TIS_PC_STS_EXPECT BIT3
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///
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/// Writes a 1 to this bit to force the TPM to re-send the response.
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///
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#define TIS_PC_STS_RETRY BIT1
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//
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// Default TimeOut value
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//
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#define TIS_TIMEOUT_A (1000 * 1000) // 1s
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#define TIS_TIMEOUT_B (2000 * 1000) // 2s
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#define TIS_TIMEOUT_C (1000 * 1000) // 1s
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#define TIS_TIMEOUT_D (1000 * 1000) // 1s
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#include <IndustryStandard/TpmTis.h>
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#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s
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@@ -546,7 +385,7 @@ Exit:
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**/
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EFI_STATUS
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EFIAPI
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DTpm2SubmitCommand (
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DTpm2TisSubmitCommand (
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IN UINT32 InputParameterBlockSize,
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IN UINT8 *InputParameterBlock,
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IN OUT UINT32 *OutputParameterBlockSize,
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@@ -571,7 +410,7 @@ DTpm2SubmitCommand (
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**/
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EFI_STATUS
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EFIAPI
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DTpm2RequestUseTpm (
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DTpm2TisRequestUseTpm (
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VOID
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)
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{
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