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ArmPlatformPkg/ArmJunoDxe: Set the platform dependent FDT device path

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The MIDR register of the CPU on which the UEFI firmware is running on
is used to infer if the platform is a Juno r0 or a Juno r1. The right
device path to the platform FDT is then stored in the
"gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths" dynamic PCD.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16939 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
2015-02-26 10:57:27 +00:00
committed by oliviermartin
parent cae7af275e
commit 7aec2926b9
8 changed files with 90 additions and 26 deletions
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4
ArmPkg/Include/Chipset/AArch64.h
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@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -44,12 +44,14 @@
#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )

5
ArmPkg/Include/Chipset/ArmV7.h
View File

@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -75,12 +75,15 @@
#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A12 0xC0D
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )