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UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

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This patch is code refactoring and doesn't change any functionality.
Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous
code, mInternalCr3 is used to pass address of page table which is
different from Cr3 register in different level of SetMemoryAttributes
function. Now remove it and pass the page table base address from the
root function parameter to simplify the code logic.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Dun Tan
2022-08-09 15:58:28 +08:00
committed by mergify[bot]
parent 83d5871184
commit 7b4754904e
4 changed files with 96 additions and 147 deletions
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30
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
View File

@@ -28,26 +28,6 @@ EnableCet (
VOID
);
/**
Get page table base address and the depth of the page table.
@param[out] Base Page table base address.
@param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level paging.
**/
VOID
GetPageTable (
OUT UINTN *Base,
OUT BOOLEAN *FiveLevels OPTIONAL
)
{
*Base = ((mInternalCr3 == 0) ?
(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
mInternalCr3);
if (FiveLevels != NULL) {
*FiveLevels = FALSE;
}
}
/**
Create PageTable for SMM use.
@@ -297,10 +277,10 @@ SetPageTableAttributes (
DEBUG ((DEBUG_INFO, "Start...\n"));
PageTableSplitted = FALSE;
GetPageTable (&PageTableBase, NULL);
L3PageTable = (UINT64 *)PageTableBase;
PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
L3PageTable = (UINT64 *)PageTableBase;
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index3 = 0; Index3 < 4; Index3++) {
@@ -309,7 +289,7 @@ SetPageTableAttributes (
continue;
}
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
@@ -323,7 +303,7 @@ SetPageTableAttributes (
continue;
}
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
}
}