MdeModulePkg/NvmExpressDxe: Fix some bugs

1) The Queue size field in create I/O submission/completion queue cmds is 0-based. the current code is 1-based.
2) a typo on allocated memory page size. it's inconsistent that some places is using 4 pages, but a place is using 6 pages.
3) a typo on PRP/SGL mechanism judgment. should directly use Psdt field rather than Opc field.
4) some platforms may not support UINT64 width access on MMIO register. Fix it to use two 32-bit width access.

Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Kinney Michael <michael.d.kinney@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14657 6f19259b-4bc3-4df7-8a09-765794883524

MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c

@@ -387,6 +387,7 @@ NvmExpressPassThru (
   UINT64                        *Prp;
   VOID                          *PrpListHost;
   UINTN                         PrpListNo;
+  UINT32                        Data;
 
   //
   // check the data fields in Packet parameter.
@@ -431,8 +432,8 @@ NvmExpressPassThru (
   //
   // Currently we only support PRP for data transfer, SGL is NOT supported.
   //
-  ASSERT ((Sq->Opc & BIT15) == 0);
-  if ((Sq->Opc & BIT15) != 0) {
+  ASSERT (Sq->Psdt == 0);
+  if (Sq->Psdt != 0) {
     DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
     return EFI_UNSUPPORTED;
   }
@@ -534,14 +535,14 @@ NvmExpressPassThru (
   // Ring the submission queue doorbell.
   //
   Private->SqTdbl[Qid].Sqt ^= 1;
-
+  Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[Qid]);
   PciIo->Mem.Write (
                PciIo,
                EfiPciIoWidthUint32,
                NVME_BAR,
                NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd),
                1,
-               &Private->SqTdbl[Qid]
+               &Data
                );
 
   Status = gBS->CreateEvent (
@@ -591,13 +592,14 @@ NvmExpressPassThru (
     NvmeDumpStatus(Cq);
   DEBUG_CODE_END();
 
+  Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[Qid]);
   PciIo->Mem.Write (
                PciIo,
                EfiPciIoWidthUint32,
                NVME_BAR,
                NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd),
                1,
-               &Private->CqHdbl[Qid]
+               &Data
                );
 
 EXIT: