MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging
5-level paging is documented in white paper:
https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf
Commit f8113e2500
changed Cpuid.h already.
This patch updates IA32_CR4 structure to include LA57 field.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
@ -5324,7 +5324,8 @@ typedef union {
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UINT32 OSXMMEXCPT:1; ///< Operating System Support for
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UINT32 OSXMMEXCPT:1; ///< Operating System Support for
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///< Unmasked SIMD Floating Point
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///< Unmasked SIMD Floating Point
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///< Exceptions.
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///< Exceptions.
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UINT32 Reserved_0:2; ///< Reserved.
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UINT32 Reserved_2:1; ///< Reserved.
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UINT32 LA57:1; ///< Linear Address 57bit.
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UINT32 VMXE:1; ///< VMX Enable
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UINT32 VMXE:1; ///< VMX Enable
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UINT32 Reserved_1:18; ///< Reserved.
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UINT32 Reserved_1:18; ///< Reserved.
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} Bits;
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} Bits;
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