OvmfPkg/SmmControl2Dxe: correct PCI_CONFIG_READ_WRITE in S3 boot script
EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to access in UEFI encoding, not in edk2/PciLib encoding. Introduce the POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() macro, and with it, store the ICH9_GEN_PMCON_1 register's address to the boot script in UEFI representation. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
@@ -19,6 +19,9 @@
|
||||
#define __Q35_MCH_ICH9_H__
|
||||
|
||||
#include <Library/PciLib.h>
|
||||
#include <Uefi/UefiBaseType.h>
|
||||
#include <Uefi/UefiSpec.h>
|
||||
#include <Protocol/PciRootBridgeIo.h>
|
||||
|
||||
//
|
||||
// Host Bridge Device ID (DID) value for Q35/MCH
|
||||
@@ -75,6 +78,9 @@
|
||||
#define POWER_MGMT_REGISTER_Q35(Offset) \
|
||||
PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
|
||||
|
||||
#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \
|
||||
EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))
|
||||
|
||||
#define ICH9_PMBASE 0x40
|
||||
#define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
|
||||
BIT10 | BIT9 | BIT8 | BIT7)
|
||||
|
Reference in New Issue
Block a user