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UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables

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v2:
  Add #define SMRR_MAX_ADDRESS to clarify SMRR requirement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Jeff Fan
2017-03-28 08:48:17 +08:00
parent 4ef6c3850e
commit 7ed6f78145
2 changed files with 29 additions and 21 deletions
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6
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
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@@ -1,7 +1,7 @@
/** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
@@ -105,6 +105,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
#define SMRR_MAX_ADDRESS BASE_4GB
typedef enum {
PageNone,
Page4K,
@@ -415,6 +417,8 @@ extern UINTN mSemaphoreSize;
extern SPIN_LOCK *mPFLock;
extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;
extern SPIN_LOCK *mMemoryMappedLock;
extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
extern UINTN mSmmCpuSmramRangeCount;
//
// Copy of the PcdPteMemoryEncryptionAddressOrMask