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add SR-IOV support in EDK II.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9269 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
htao
2009-09-16 09:32:06 +00:00
parent fd53905e69
commit 7fc72ecb0d
11 changed files with 988 additions and 10 deletions
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32
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
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@ -215,6 +215,10 @@ RegisterPciDevice (
EFI_PCI_IO_PROTOCOL *PciIo;
UINT8 Data8;
BOOLEAN HasEfiImage;
PCI_IO_DEVICE *ParrentPciIoDevice;
EFI_PCI_IO_PROTOCOL *ParrentPciIo;
UINT16 Data16;
UINT32 Data32;
//
// Install the pciio protocol, device path protocol
@ -251,7 +255,35 @@ RegisterPciDevice (
PciIo = &(PciIoDevice->PciIo);
Data8 = PCI_INT_LINE_UNKNOWN;
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
//
// PCI-IOV programming
//
if (((FeaturePcdGet(PcdAriSupport) & EFI_PCI_IOV_POLICY_ARI) != 0) && (PciIoDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport) & EFI_PCI_IOV_POLICY_SRIOV) != 0) &&
(PciIoDevice->SrIovCapabilityOffset != 0)) {
//
// Check its parrent ARI forwarding capability
//
ParrentPciIoDevice = PciIoDevice->Parent;
ParrentPciIo = &(ParrentPciIoDevice->PciIo);
ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, 1, &Data32);
if (Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) {
//
// ARI forward support in bridge, so enable it.
//
ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
ParrentPciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
//
// Set ARI Capable Hierarchy for device
//
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
}
}
//
// Process OpRom
//