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Add missing PCI class code definition.

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PCI22/PCI23/PCI30 spec were reviewed and the missing definitions were added to accordingly Pci22.h/Pci23.h/Pci30.h.
All other class code definitions that are not defined in PCI Local Bus specification but in PCI Code and ID Assignment specification are defined in PciCodeId.h.

Signed-off-by: Ruiyu Ni<ruiyu.ni@intel.com>
Reviewed-by: Liming Gao<liming.gao@intel.com>
Reviewed-by: Hot Tian<hot.tian@intel.com>
Reviewed-by: Elvin Li<elvin.li@intel.com>
Reviewed-by: Feng Tian<feng.tian@intel.com>
Reviewed-by: Jiewen Yao<jiewen.yao@intel.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13919 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
niruiyu
2012-11-02 06:13:14 +00:00
parent 44c56530b3
commit 826a66d4c0
5 changed files with 172 additions and 10 deletions
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51
MdePkg/Include/IndustryStandard/Pci23.h
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@@ -1,7 +1,7 @@
/** @file
Support for PCI 2.3 standard.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -26,12 +26,61 @@
#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30
///@}
///
/// PCI_CLASS_NETWORK, Base Class 02h.
///
///@{
#define PCI_CLASS_NETWORK_WORLDFIP 0x05
#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
///@}
///
/// PCI_CLASS_BRIDGE, Base Class 06h.
///
///@{
#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09
#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40
#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A
///@}
///
/// PCI_CLASS_SCC, Base Class 07h.
///
///@{
#define PCI_SUBCLASS_GPIB 0x04
#define PCI_SUBCLASS_SMART_CARD 0x05
///@}
///
/// PCI_CLASS_SERIAL, Base Class 0Ch.
///
///@{
#define PCI_IF_EHCI 0x20
#define PCI_CLASS_SERIAL_IB 0x06
#define PCI_CLASS_SERIAL_IPMI 0x07
#define PCI_IF_IPMI_SMIC 0x00
#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style
#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer
#define PCI_CLASS_SERIAL_SERCOS 0x08
#define PCI_CLASS_SERIAL_CANBUS 0x09
///@}
///
/// PCI_CLASS_WIRELESS, Base Class 0Dh.
///
///@{
#define PCI_SUBCLASS_BLUETOOTH 0x11
#define PCI_SUBCLASS_BROADBAND 0x12
///@}
///
/// PCI_CLASS_DPIO, Base Class 11h.
///
///@{
#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01
#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20
///@}
///