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Add missing PCI class code definition.

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PCI22/PCI23/PCI30 spec were reviewed and the missing definitions were added to accordingly Pci22.h/Pci23.h/Pci30.h.
All other class code definitions that are not defined in PCI Local Bus specification but in PCI Code and ID Assignment specification are defined in PciCodeId.h.

Signed-off-by: Ruiyu Ni<ruiyu.ni@intel.com>
Reviewed-by: Liming Gao<liming.gao@intel.com>
Reviewed-by: Hot Tian<hot.tian@intel.com>
Reviewed-by: Elvin Li<elvin.li@intel.com>
Reviewed-by: Feng Tian<feng.tian@intel.com>
Reviewed-by: Jiewen Yao<jiewen.yao@intel.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13919 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
niruiyu
2012-11-02 06:13:14 +00:00
parent 44c56530b3
commit 826a66d4c0
5 changed files with 172 additions and 10 deletions
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100
MdePkg/Include/IndustryStandard/PciCodeId.h Normal file
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/** @file
The file lists the PCI class codes only defined in PCI code and ID assignment specification
revision 1.3.
Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PCI_CODE_ID_H__
#define __PCI_CODE_ID_H__
///
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
///
///@{
#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
#define PCI_CLASS_MASS_STORAGE_SAS 0x07
#define PCI_IF_MASS_STORAGE_SAS 0x00
#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
///@}
///
/// PCI_CLASS_NETWORK, Base Class 02h.
///
///@{
#define PCI_CLASS_NETWORK_INFINIBAND 0x07
///@}
///
/// PCI_CLASS_MEDIA, Base Class 04h.
///
///@{
#define PCI_CLASS_MEDIA_MIXED_MODE 0x03
///@}
///
/// PCI_CLASS_BRIDGE, Base Class 06h.
///
///@{
#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
///@}
///
/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.
///
///@{
#define PCI_IF_HPET 0x03
#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
#define PCI_SUBCLASS_IOMMU 0x06
///@}
///
/// PCI_CLASS_PROCESSOR, Base Class 0Bh.
///
///@{
#define PCI_SUBCLASS_PROC_OTHER 0x80
///@}
///
/// PCI_CLASS_SERIAL, Base Class 0Ch.
///
///@{
#define PCI_IF_XHCI 0x30
#define PCI_CLASS_SERIAL_OTHER 0x80
///@}
///
/// PCI_CLASS_SATELLITE, Base Class 0Fh.
///
///@{
#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
///@}
///
/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.
///
///@{
#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12
///@}
#endif