OvmfPkg/AcpiTables: Change the ACPI PM Base Adress to 0xb000

0xb000 is the address normally used with QEMU.

0x400 also appears to conflict with some debug I/O ports
used by QEMU.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13279 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jljusten 2012-05-04 15:02:33 +00:00
parent 9b167857a4
commit 834d3ccda0
3 changed files with 5 additions and 5 deletions

View File

@ -364,11 +364,11 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) {
IO (Decode16, 0x278, 0x278, 0x00, 0x08) IO (Decode16, 0x278, 0x278, 0x00, 0x08)
IO (Decode16, 0x370, 0x370, 0x00, 0x02) IO (Decode16, 0x370, 0x370, 0x00, 0x02)
IO (Decode16, 0x378, 0x378, 0x00, 0x08) IO (Decode16, 0x378, 0x378, 0x00, 0x08)
IO (Decode16, 0x400, 0x400, 0x00, 0x40) // PMBLK1
IO (Decode16, 0x440, 0x440, 0x00, 0x10) IO (Decode16, 0x440, 0x440, 0x00, 0x10)
IO (Decode16, 0x678, 0x678, 0x00, 0x08) IO (Decode16, 0x678, 0x678, 0x00, 0x08)
IO (Decode16, 0x778, 0x778, 0x00, 0x08) IO (Decode16, 0x778, 0x778, 0x00, 0x08)
IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK
IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1
Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC
Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000) Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000)
}) })

View File

@ -33,12 +33,12 @@
#define ACPI_ENABLE 0 #define ACPI_ENABLE 0
#define ACPI_DISABLE 0 #define ACPI_DISABLE 0
#define S4BIOS_REQ 0x00 #define S4BIOS_REQ 0x00
#define PM1a_EVT_BLK 0x00000400 #define PM1a_EVT_BLK 0x0000b000
#define PM1b_EVT_BLK 0x00000000 #define PM1b_EVT_BLK 0x00000000
#define PM1a_CNT_BLK 0x00000404 #define PM1a_CNT_BLK 0x0000b004
#define PM1b_CNT_BLK 0x00000000 #define PM1b_CNT_BLK 0x00000000
#define PM2_CNT_BLK 0x00000022 #define PM2_CNT_BLK 0x00000022
#define PM_TMR_BLK 0x00000408 #define PM_TMR_BLK 0x0000b008
#define GPE0_BLK 0x0000afe0 #define GPE0_BLK 0x0000afe0
#define GPE1_BLK 0x00000000 #define GPE1_BLK 0x00000000
#define PM1_EVT_LEN 0x04 #define PM1_EVT_LEN 0x04

View File

@ -24,7 +24,7 @@
// //
// PIIX4 Power Management Base Address // PIIX4 Power Management Base Address
// //
UINT32 mPmba = 0x400; UINT32 mPmba = 0xb000;
#define PCI_BAR_IO 0x1 #define PCI_BAR_IO 0x1
#define ACPI_TIMER_FREQUENCY 3579545 #define ACPI_TIMER_FREQUENCY 3579545