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MdeModulePkg: Change use of EFI_D_* to DEBUG_*

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3739

Update all use of EFI_D_* defines in DEBUG() macros to DEBUG_* defines.

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael D Kinney
2021-11-16 19:21:29 -08:00
committed by mergify[bot]
parent 917e98f3e5
commit 87000d7708
146 changed files with 1560 additions and 1619 deletions
Download Patch File Download Diff File Expand all files Collapse all files

53
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
View File

@@ -85,7 +85,7 @@ EhcGetCapability (
*PortNumber = (UINT8) (Ehc->HcStructParams & HCSP_NPORTS);
*Is64BitCapable = (UINT8) Ehc->Support64BitDma;
DEBUG ((EFI_D_INFO, "EhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
DEBUG ((DEBUG_INFO, "EhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
gBS->RestoreTPL (OldTpl);
return EFI_SUCCESS;
@@ -181,7 +181,7 @@ EhcReset (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "EhcReset: exit status %r\n", Status));
DEBUG ((DEBUG_INFO, "EhcReset: exit status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
}
@@ -225,7 +225,7 @@ EhcGetState (
gBS->RestoreTPL (OldTpl);
DEBUG ((EFI_D_INFO, "EhcGetState: current state %d\n", *State));
DEBUG ((DEBUG_INFO, "EhcGetState: current state %d\n", *State));
return EFI_SUCCESS;
}
@@ -299,7 +299,7 @@ EhcSetState (
Status = EFI_INVALID_PARAMETER;
}
DEBUG ((EFI_D_INFO, "EhcSetState: exit status %r\n", Status));
DEBUG ((DEBUG_INFO, "EhcSetState: exit status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
}
@@ -470,7 +470,7 @@ EhcSetRootHubPortFeature (
Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_INFO, "EhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
DEBUG ((DEBUG_INFO, "EhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
break;
}
}
@@ -503,7 +503,7 @@ EhcSetRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "EhcSetRootHubPortFeature: exit status %r\n", Status));
DEBUG ((DEBUG_INFO, "EhcSetRootHubPortFeature: exit status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -638,7 +638,7 @@ EhcClearRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "EhcClearRootHubPortFeature: exit status %r\n", Status));
DEBUG ((DEBUG_INFO, "EhcClearRootHubPortFeature: exit status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
}
@@ -729,7 +729,7 @@ EhcControlTransfer (
*TransferResult = EFI_USB_ERR_SYSTEM;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
DEBUG ((EFI_D_ERROR, "EhcControlTransfer: HC halted at entrance\n"));
DEBUG ((DEBUG_ERROR, "EhcControlTransfer: HC halted at entrance\n"));
EhcAckAllInterrupt (Ehc);
goto ON_EXIT;
@@ -765,7 +765,7 @@ EhcControlTransfer (
);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "EhcControlTransfer: failed to create URB"));
DEBUG ((DEBUG_ERROR, "EhcControlTransfer: failed to create URB"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
@@ -794,7 +794,7 @@ ON_EXIT:
gBS->RestoreTPL (OldTpl);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "EhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
return Status;
@@ -878,7 +878,7 @@ EhcBulkTransfer (
Status = EFI_DEVICE_ERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
DEBUG ((EFI_D_ERROR, "EhcBulkTransfer: HC is halted\n"));
DEBUG ((DEBUG_ERROR, "EhcBulkTransfer: HC is halted\n"));
EhcAckAllInterrupt (Ehc);
goto ON_EXIT;
@@ -908,7 +908,7 @@ EhcBulkTransfer (
);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "EhcBulkTransfer: failed to create URB\n"));
DEBUG ((DEBUG_ERROR, "EhcBulkTransfer: failed to create URB\n"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
@@ -934,7 +934,7 @@ ON_EXIT:
gBS->RestoreTPL (OldTpl);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "EhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
return Status;
@@ -1023,14 +1023,14 @@ EhcAsyncInterruptTransfer (
if (!IsNewTransfer) {
Status = EhciDelAsyncIntTransfer (Ehc, DeviceAddress, EndPointAddress, DataToggle);
DEBUG ((EFI_D_INFO, "EhcAsyncInterruptTransfer: remove old transfer - %r\n", Status));
DEBUG ((DEBUG_INFO, "EhcAsyncInterruptTransfer: remove old transfer - %r\n", Status));
goto ON_EXIT;
}
Status = EFI_SUCCESS;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
DEBUG ((EFI_D_ERROR, "EhcAsyncInterruptTransfer: HC is halt\n"));
DEBUG ((DEBUG_ERROR, "EhcAsyncInterruptTransfer: HC is halt\n"));
EhcAckAllInterrupt (Ehc);
Status = EFI_DEVICE_ERROR;
@@ -1139,7 +1139,7 @@ EhcSyncInterruptTransfer (
Status = EFI_DEVICE_ERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
DEBUG ((EFI_D_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
DEBUG ((DEBUG_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
EhcAckAllInterrupt (Ehc);
goto ON_EXIT;
@@ -1165,7 +1165,7 @@ EhcSyncInterruptTransfer (
);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "EhcSyncInterruptTransfer: failed to create URB\n"));
DEBUG ((DEBUG_ERROR, "EhcSyncInterruptTransfer: failed to create URB\n"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
@@ -1189,7 +1189,7 @@ ON_EXIT:
gBS->RestoreTPL (OldTpl);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "EhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
return Status;
@@ -1562,7 +1562,7 @@ EhcCreateUsb2Hc (
Ehc->HcCapParams = EhcReadCapRegister (Ehc, EHC_HCCPARAMS_OFFSET);
Ehc->CapLen = EhcReadCapRegister (Ehc, EHC_CAPLENGTH_OFFSET) & 0x0FF;
DEBUG ((EFI_D_INFO, "EhcCreateUsb2Hc: capability length %d\n", Ehc->CapLen));
DEBUG ((DEBUG_INFO, "EhcCreateUsb2Hc: capability length %d\n", Ehc->CapLen));
//
// EHCI Controllers with a CapLen of 0 are ignored.
@@ -1723,7 +1723,7 @@ EhcDriverBindingStart (
}
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcDriverBindingStart: failed to enable controller\n"));
DEBUG ((DEBUG_ERROR, "EhcDriverBindingStart: failed to enable controller\n"));
goto CLOSE_PCIIO;
}
@@ -1834,7 +1834,7 @@ EhcDriverBindingStart (
Ehc = EhcCreateUsb2Hc (PciIo, HcDevicePath, OriginalPciAttributes);
if (Ehc == NULL) {
DEBUG ((EFI_D_ERROR, "EhcDriverBindingStart: failed to create USB2_HC\n"));
DEBUG ((DEBUG_ERROR, "EhcDriverBindingStart: failed to create USB2_HC\n"));
Status = EFI_OUT_OF_RESOURCES;
goto CLOSE_PCIIO;
@@ -1854,7 +1854,7 @@ EhcDriverBindingStart (
if (!EFI_ERROR (Status)) {
Ehc->Support64BitDma = TRUE;
} else {
DEBUG ((EFI_D_WARN,
DEBUG ((DEBUG_WARN,
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
__FUNCTION__, Controller, Status));
}
@@ -1868,7 +1868,7 @@ EhcDriverBindingStart (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
DEBUG ((DEBUG_ERROR, "EhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
goto FREE_POOL;
}
@@ -1887,7 +1887,7 @@ EhcDriverBindingStart (
Status = EhcInitHC (Ehc);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcDriverBindingStart: failed to init host controller\n"));
DEBUG ((DEBUG_ERROR, "EhcDriverBindingStart: failed to init host controller\n"));
goto UNINSTALL_USBHC;
}
@@ -1897,7 +1897,7 @@ EhcDriverBindingStart (
Status = gBS->SetTimer (Ehc->PollTimer, TimerPeriodic, EHC_ASYNC_POLL_INTERVAL);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcDriverBindingStart: failed to start async interrupt monitor\n"));
DEBUG ((DEBUG_ERROR, "EhcDriverBindingStart: failed to start async interrupt monitor\n"));
EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
goto UNINSTALL_USBHC;
@@ -1938,7 +1938,7 @@ EhcDriverBindingStart (
);
DEBUG ((EFI_D_INFO, "EhcDriverBindingStart: EHCI started for controller @ %p\n", Controller));
DEBUG ((DEBUG_INFO, "EhcDriverBindingStart: EHCI started for controller @ %p\n", Controller));
return EFI_SUCCESS;
UNINSTALL_USBHC:
@@ -2083,4 +2083,3 @@ EhcDriverBindingStop (
return EFI_SUCCESS;
}

118
MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c
View File

@@ -23,38 +23,38 @@ EhcDumpStatus (
)
{
if (EHC_BIT_IS_SET (State, QTD_STAT_DO_PING)) {
DEBUG ((EFI_D_VERBOSE, " Do_Ping"));
DEBUG ((DEBUG_VERBOSE, " Do_Ping"));
} else {
DEBUG ((EFI_D_VERBOSE, " Do_Out"));
DEBUG ((DEBUG_VERBOSE, " Do_Out"));
}
if (EHC_BIT_IS_SET (State, QTD_STAT_DO_CS)) {
DEBUG ((EFI_D_VERBOSE, " Do_CS"));
DEBUG ((DEBUG_VERBOSE, " Do_CS"));
} else {
DEBUG ((EFI_D_VERBOSE, " Do_SS"));
DEBUG ((DEBUG_VERBOSE, " Do_SS"));
}
if (EHC_BIT_IS_SET (State, QTD_STAT_TRANS_ERR)) {
DEBUG ((EFI_D_VERBOSE, " Transfer_Error"));
DEBUG ((DEBUG_VERBOSE, " Transfer_Error"));
}
if (EHC_BIT_IS_SET (State, QTD_STAT_BABBLE_ERR)) {
DEBUG ((EFI_D_VERBOSE, " Babble_Error"));
DEBUG ((DEBUG_VERBOSE, " Babble_Error"));
}
if (EHC_BIT_IS_SET (State, QTD_STAT_BUFF_ERR)) {
DEBUG ((EFI_D_VERBOSE, " Buffer_Error"));
DEBUG ((DEBUG_VERBOSE, " Buffer_Error"));
}
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
DEBUG ((EFI_D_VERBOSE, " Halted"));
DEBUG ((DEBUG_VERBOSE, " Halted"));
}
if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
DEBUG ((EFI_D_VERBOSE, " Active"));
DEBUG ((DEBUG_VERBOSE, " Active"));
}
DEBUG ((EFI_D_VERBOSE, "\n"));
DEBUG ((DEBUG_VERBOSE, "\n"));
}
@@ -75,37 +75,37 @@ EhcDumpQtd (
UINTN Index;
if (Msg != NULL) {
DEBUG ((EFI_D_VERBOSE, Msg));
DEBUG ((DEBUG_VERBOSE, Msg));
}
DEBUG ((EFI_D_VERBOSE, "Queue TD @ 0x%p, data length %d\n", Qtd, (UINT32)Qtd->DataLen));
DEBUG ((DEBUG_VERBOSE, "Queue TD @ 0x%p, data length %d\n", Qtd, (UINT32)Qtd->DataLen));
QtdHw = &Qtd->QtdHw;
DEBUG ((EFI_D_VERBOSE, "Next QTD : %x\n", QtdHw->NextQtd));
DEBUG ((EFI_D_VERBOSE, "AltNext QTD : %x\n", QtdHw->AltNext));
DEBUG ((EFI_D_VERBOSE, "Status : %x\n", QtdHw->Status));
DEBUG ((DEBUG_VERBOSE, "Next QTD : %x\n", QtdHw->NextQtd));
DEBUG ((DEBUG_VERBOSE, "AltNext QTD : %x\n", QtdHw->AltNext));
DEBUG ((DEBUG_VERBOSE, "Status : %x\n", QtdHw->Status));
EhcDumpStatus (QtdHw->Status);
if (QtdHw->Pid == QTD_PID_SETUP) {
DEBUG ((EFI_D_VERBOSE, "PID : Setup\n"));
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
} else if (QtdHw->Pid == QTD_PID_INPUT) {
DEBUG ((EFI_D_VERBOSE, "PID : IN\n"));
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
} else if (QtdHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((EFI_D_VERBOSE, "PID : OUT\n"));
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
}
DEBUG ((EFI_D_VERBOSE, "Error Count : %d\n", QtdHw->ErrCnt));
DEBUG ((EFI_D_VERBOSE, "Current Page : %d\n", QtdHw->CurPage));
DEBUG ((EFI_D_VERBOSE, "IOC : %d\n", QtdHw->Ioc));
DEBUG ((EFI_D_VERBOSE, "Total Bytes : %d\n", QtdHw->TotalBytes));
DEBUG ((EFI_D_VERBOSE, "Data Toggle : %d\n", QtdHw->DataToggle));
DEBUG ((DEBUG_VERBOSE, "Error Count : %d\n", QtdHw->ErrCnt));
DEBUG ((DEBUG_VERBOSE, "Current Page : %d\n", QtdHw->CurPage));
DEBUG ((DEBUG_VERBOSE, "IOC : %d\n", QtdHw->Ioc));
DEBUG ((DEBUG_VERBOSE, "Total Bytes : %d\n", QtdHw->TotalBytes));
DEBUG ((DEBUG_VERBOSE, "Data Toggle : %d\n", QtdHw->DataToggle));
for (Index = 0; Index < 5; Index++) {
DEBUG ((EFI_D_VERBOSE, "Page[%d] : 0x%x\n", (UINT32)Index, QtdHw->Page[Index]));
DEBUG ((DEBUG_VERBOSE, "Page[%d] : 0x%x\n", (UINT32)Index, QtdHw->Page[Index]));
}
}
@@ -131,60 +131,60 @@ EhcDumpQh (
UINTN Index;
if (Msg != NULL) {
DEBUG ((EFI_D_VERBOSE, Msg));
DEBUG ((DEBUG_VERBOSE, Msg));
}
DEBUG ((EFI_D_VERBOSE, "Queue head @ 0x%p, interval %ld, next qh %p\n",
DEBUG ((DEBUG_VERBOSE, "Queue head @ 0x%p, interval %ld, next qh %p\n",
Qh, (UINT64)Qh->Interval, Qh->NextQh));
QhHw = &Qh->QhHw;
DEBUG ((EFI_D_VERBOSE, "Hoziontal link: %x\n", QhHw->HorizonLink));
DEBUG ((EFI_D_VERBOSE, "Device address: %d\n", QhHw->DeviceAddr));
DEBUG ((EFI_D_VERBOSE, "Inactive : %d\n", QhHw->Inactive));
DEBUG ((EFI_D_VERBOSE, "EP number : %d\n", QhHw->EpNum));
DEBUG ((EFI_D_VERBOSE, "EP speed : %d\n", QhHw->EpSpeed));
DEBUG ((EFI_D_VERBOSE, "DT control : %d\n", QhHw->DtCtrl));
DEBUG ((EFI_D_VERBOSE, "Reclaim head : %d\n", QhHw->ReclaimHead));
DEBUG ((EFI_D_VERBOSE, "Max packet len: %d\n", QhHw->MaxPacketLen));
DEBUG ((EFI_D_VERBOSE, "Ctrl EP : %d\n", QhHw->CtrlEp));
DEBUG ((EFI_D_VERBOSE, "Nak reload : %d\n", QhHw->NakReload));
DEBUG ((DEBUG_VERBOSE, "Hoziontal link: %x\n", QhHw->HorizonLink));
DEBUG ((DEBUG_VERBOSE, "Device address: %d\n", QhHw->DeviceAddr));
DEBUG ((DEBUG_VERBOSE, "Inactive : %d\n", QhHw->Inactive));
DEBUG ((DEBUG_VERBOSE, "EP number : %d\n", QhHw->EpNum));
DEBUG ((DEBUG_VERBOSE, "EP speed : %d\n", QhHw->EpSpeed));
DEBUG ((DEBUG_VERBOSE, "DT control : %d\n", QhHw->DtCtrl));
DEBUG ((DEBUG_VERBOSE, "Reclaim head : %d\n", QhHw->ReclaimHead));
DEBUG ((DEBUG_VERBOSE, "Max packet len: %d\n", QhHw->MaxPacketLen));
DEBUG ((DEBUG_VERBOSE, "Ctrl EP : %d\n", QhHw->CtrlEp));
DEBUG ((DEBUG_VERBOSE, "Nak reload : %d\n", QhHw->NakReload));
DEBUG ((EFI_D_VERBOSE, "SMask : %x\n", QhHw->SMask));
DEBUG ((EFI_D_VERBOSE, "CMask : %x\n", QhHw->CMask));
DEBUG ((EFI_D_VERBOSE, "Hub address : %d\n", QhHw->HubAddr));
DEBUG ((EFI_D_VERBOSE, "Hub port : %d\n", QhHw->PortNum));
DEBUG ((EFI_D_VERBOSE, "Multiplier : %d\n", QhHw->Multiplier));
DEBUG ((DEBUG_VERBOSE, "SMask : %x\n", QhHw->SMask));
DEBUG ((DEBUG_VERBOSE, "CMask : %x\n", QhHw->CMask));
DEBUG ((DEBUG_VERBOSE, "Hub address : %d\n", QhHw->HubAddr));
DEBUG ((DEBUG_VERBOSE, "Hub port : %d\n", QhHw->PortNum));
DEBUG ((DEBUG_VERBOSE, "Multiplier : %d\n", QhHw->Multiplier));
DEBUG ((EFI_D_VERBOSE, "Cur QTD : %x\n", QhHw->CurQtd));
DEBUG ((DEBUG_VERBOSE, "Cur QTD : %x\n", QhHw->CurQtd));
DEBUG ((EFI_D_VERBOSE, "Next QTD : %x\n", QhHw->NextQtd));
DEBUG ((EFI_D_VERBOSE, "AltNext QTD : %x\n", QhHw->AltQtd));
DEBUG ((EFI_D_VERBOSE, "Status : %x\n", QhHw->Status));
DEBUG ((DEBUG_VERBOSE, "Next QTD : %x\n", QhHw->NextQtd));
DEBUG ((DEBUG_VERBOSE, "AltNext QTD : %x\n", QhHw->AltQtd));
DEBUG ((DEBUG_VERBOSE, "Status : %x\n", QhHw->Status));
EhcDumpStatus (QhHw->Status);
if (QhHw->Pid == QTD_PID_SETUP) {
DEBUG ((EFI_D_VERBOSE, "PID : Setup\n"));
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
} else if (QhHw->Pid == QTD_PID_INPUT) {
DEBUG ((EFI_D_VERBOSE, "PID : IN\n"));
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
} else if (QhHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((EFI_D_VERBOSE, "PID : OUT\n"));
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
}
DEBUG ((EFI_D_VERBOSE, "Error Count : %d\n", QhHw->ErrCnt));
DEBUG ((EFI_D_VERBOSE, "Current Page : %d\n", QhHw->CurPage));
DEBUG ((EFI_D_VERBOSE, "IOC : %d\n", QhHw->Ioc));
DEBUG ((EFI_D_VERBOSE, "Total Bytes : %d\n", QhHw->TotalBytes));
DEBUG ((EFI_D_VERBOSE, "Data Toggle : %d\n", QhHw->DataToggle));
DEBUG ((DEBUG_VERBOSE, "Error Count : %d\n", QhHw->ErrCnt));
DEBUG ((DEBUG_VERBOSE, "Current Page : %d\n", QhHw->CurPage));
DEBUG ((DEBUG_VERBOSE, "IOC : %d\n", QhHw->Ioc));
DEBUG ((DEBUG_VERBOSE, "Total Bytes : %d\n", QhHw->TotalBytes));
DEBUG ((DEBUG_VERBOSE, "Data Toggle : %d\n", QhHw->DataToggle));
for (Index = 0; Index < 5; Index++) {
DEBUG ((EFI_D_VERBOSE, "Page[%d] : 0x%x\n", Index, QhHw->Page[Index]));
DEBUG ((DEBUG_VERBOSE, "Page[%d] : 0x%x\n", Index, QhHw->Page[Index]));
}
DEBUG ((EFI_D_VERBOSE, "\n"));
DEBUG ((DEBUG_VERBOSE, "\n"));
BASE_LIST_FOR_EACH (Entry, &Qh->Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);
@@ -214,13 +214,11 @@ EhcDumpBuf (
for (Index = 0; Index < Len; Index++) {
if (Index % 16 == 0) {
DEBUG ((EFI_D_VERBOSE,"\n"));
DEBUG ((DEBUG_VERBOSE,"\n"));
}
DEBUG ((EFI_D_VERBOSE, "%02x ", Buf[Index]));
DEBUG ((DEBUG_VERBOSE, "%02x ", Buf[Index]));
}
DEBUG ((EFI_D_VERBOSE, "\n"));
DEBUG ((DEBUG_VERBOSE, "\n"));
}

14
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
View File

@@ -40,7 +40,7 @@ EhcReadCapRegister (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcReadCapRegister: Pci Io read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "EhcReadCapRegister: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFFFF;
}
@@ -76,7 +76,7 @@ EhcReadDbgRegister (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcReadDbgRegister: Pci Io read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "EhcReadDbgRegister: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFFFF;
}
@@ -168,7 +168,7 @@ EhcReadOpReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "EhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFF;
}
@@ -205,7 +205,7 @@ EhcWriteOpReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "EhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -310,7 +310,7 @@ EhcClearLegacySupport (
UINT32 Value;
UINT32 TimeOut;
DEBUG ((EFI_D_INFO, "EhcClearLegacySupport: called to clear legacy support\n"));
DEBUG ((DEBUG_INFO, "EhcClearLegacySupport: called to clear legacy support\n"));
PciIo = Ehc->PciIo;
ExtendCap = (Ehc->HcCapParams >> 8) & 0xFF;
@@ -654,14 +654,14 @@ EhcInitHC (
Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcInitHC: failed to enable period schedule\n"));
DEBUG ((DEBUG_ERROR, "EhcInitHC: failed to enable period schedule\n"));
return Status;
}
Status = EhcEnableAsyncSchd (Ehc, EHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcInitHC: failed to enable async schedule\n"));
DEBUG ((DEBUG_ERROR, "EhcInitHC: failed to enable async schedule\n"));
return Status;
}

12
MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c
View File

@@ -377,7 +377,7 @@ EhcUnlinkQhFromAsync (
Status = EhcSetAndWaitDoorBell (Ehc, EHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcUnlinkQhFromAsync: Failed to synchronize with doorbell\n"));
DEBUG ((DEBUG_ERROR, "EhcUnlinkQhFromAsync: Failed to synchronize with doorbell\n"));
}
}
@@ -636,13 +636,13 @@ EhcCheckUrbResult (
//
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
if (QtdHw->AltNext == QTD_LINK (PciAddr, FALSE)) {
DEBUG ((EFI_D_VERBOSE, "EhcCheckUrbResult: Short packet read, break\n"));
DEBUG ((DEBUG_VERBOSE, "EhcCheckUrbResult: Short packet read, break\n"));
Finished = TRUE;
goto ON_EXIT;
}
DEBUG ((EFI_D_VERBOSE, "EhcCheckUrbResult: Short packet read, continue\n"));
DEBUG ((DEBUG_VERBOSE, "EhcCheckUrbResult: Short packet read, continue\n"));
}
}
}
@@ -713,13 +713,13 @@ EhcExecTransfer (
}
if (!Finished) {
DEBUG ((EFI_D_ERROR, "EhcExecTransfer: transfer not finished in %dms\n", (UINT32)TimeOut));
DEBUG ((DEBUG_ERROR, "EhcExecTransfer: transfer not finished in %dms\n", (UINT32)TimeOut));
EhcDumpQh (Urb->Qh, NULL, FALSE);
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
DEBUG ((EFI_D_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));
DEBUG ((DEBUG_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));
EhcDumpQh (Urb->Qh, NULL, FALSE);
Status = EFI_DEVICE_ERROR;
@@ -1069,7 +1069,7 @@ EhcMonitorAsyncRequests (
//
Status = EhcFlushAsyncIntMap (Ehc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "EhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
DEBUG ((DEBUG_ERROR, "EhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
}
//

2
MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c
View File

@@ -470,7 +470,7 @@ UsbHcAllocateMem (
NewBlock = UsbHcAllocMemBlock (Pool, Pages);
if (NewBlock == NULL) {
DEBUG ((EFI_D_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
DEBUG ((DEBUG_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
return NULL;
}

34
MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c
View File

@@ -76,7 +76,7 @@ AtapiPeimEntry (
AtapiBlkIoDev->PpiDescriptor2.Guid = &gEfiPeiVirtualBlockIo2PpiGuid;
AtapiBlkIoDev->PpiDescriptor2.Ppi = &AtapiBlkIoDev->AtapiBlkIo2;
DEBUG ((EFI_D_INFO, "Atatpi Device Count is %d\n", AtapiBlkIoDev->DeviceCount));
DEBUG ((DEBUG_INFO, "Atatpi Device Count is %d\n", AtapiBlkIoDev->DeviceCount));
if (AtapiBlkIoDev->DeviceCount != 0) {
Status = PeiServicesInstallPpi (&AtapiBlkIoDev->PpiDescriptor);
if (EFI_ERROR (Status)) {
@@ -189,11 +189,11 @@ AtapiGetBlockDeviceMediaInfo (
//
// probe media and retrieve latest media information
//
DEBUG ((EFI_D_INFO, "Atatpi GetInfo DevicePosition is %d\n", AtapiBlkIoDev->DeviceInfo[Index].DevicePosition));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo DeviceType is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.DeviceType));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo MediaPresent is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.MediaPresent));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo BlockSize is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.BlockSize));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo LastBlock is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.LastBlock));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo DevicePosition is %d\n", AtapiBlkIoDev->DeviceInfo[Index].DevicePosition));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo DeviceType is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.DeviceType));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo MediaPresent is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.MediaPresent));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo BlockSize is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.BlockSize));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo LastBlock is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.LastBlock));
Status = DetectMedia (
AtapiBlkIoDev,
@@ -205,11 +205,11 @@ AtapiGetBlockDeviceMediaInfo (
return EFI_DEVICE_ERROR;
}
DEBUG ((EFI_D_INFO, "Atatpi GetInfo DevicePosition is %d\n", AtapiBlkIoDev->DeviceInfo[Index].DevicePosition));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo DeviceType is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.DeviceType));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo MediaPresent is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.MediaPresent));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo BlockSize is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.BlockSize));
DEBUG ((EFI_D_INFO, "Atatpi GetInfo LastBlock is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.LastBlock));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo DevicePosition is %d\n", AtapiBlkIoDev->DeviceInfo[Index].DevicePosition));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo DeviceType is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.DeviceType));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo MediaPresent is %d\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.MediaPresent));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo BlockSize is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.BlockSize));
DEBUG ((DEBUG_INFO, "Atatpi GetInfo LastBlock is 0x%x\n", AtapiBlkIoDev->DeviceInfo[Index].MediaInfo.LastBlock));
//
// Get media info from AtapiBlkIoDev
@@ -549,7 +549,7 @@ AtapiEnumerateDevices (
// Allow SATA Devices to spin-up. This is needed if
// SEC and PEI phase is too short, for example Release Build.
//
DEBUG ((EFI_D_INFO, "Delay for %d seconds for SATA devices to spin-up\n", PcdGet16 (PcdSataSpinUpDelayInSecForRecoveryPath)));
DEBUG ((DEBUG_INFO, "Delay for %d seconds for SATA devices to spin-up\n", PcdGet16 (PcdSataSpinUpDelayInSecForRecoveryPath)));
MicroSecondDelay (PcdGet16 (PcdSataSpinUpDelayInSecForRecoveryPath) * 1000 * 1000); //
//
@@ -600,10 +600,10 @@ AtapiEnumerateDevices (
CopyMem (&(AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo), &MediaInfo, sizeof (MediaInfo));
CopyMem (&(AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo2), &MediaInfo2, sizeof (MediaInfo2));
DEBUG ((EFI_D_INFO, "Atatpi Device Position is %d\n", DevicePosition));
DEBUG ((EFI_D_INFO, "Atatpi DeviceType is %d\n", MediaInfo.DeviceType));
DEBUG ((EFI_D_INFO, "Atatpi MediaPresent is %d\n", MediaInfo.MediaPresent));
DEBUG ((EFI_D_INFO, "Atatpi BlockSize is 0x%x\n", MediaInfo.BlockSize));
DEBUG ((DEBUG_INFO, "Atatpi Device Position is %d\n", DevicePosition));
DEBUG ((DEBUG_INFO, "Atatpi DeviceType is %d\n", MediaInfo.DeviceType));
DEBUG ((DEBUG_INFO, "Atatpi MediaPresent is %d\n", MediaInfo.MediaPresent));
DEBUG ((DEBUG_INFO, "Atatpi BlockSize is 0x%x\n", MediaInfo.BlockSize));
if (EFI_ERROR (Status)) {
AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo.MediaPresent = FALSE;
@@ -1764,7 +1764,7 @@ DetectMedia (
SenseBuffers,
&SenseCounts
);
DEBUG ((EFI_D_INFO, "Atapi Request Sense Count is %d\n", SenseCounts));
DEBUG ((DEBUG_INFO, "Atapi Request Sense Count is %d\n", SenseCounts));
if (IsDeviceStateUnclear (SenseBuffers, SenseCounts) || IsNoMedia (SenseBuffers, SenseCounts)) {
//
// We are not sure whether the media is present or not, try again

18
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
View File

@@ -271,11 +271,11 @@ EnumerateNvmeDevNamespace (
//
// Dump NvmExpress Identify Namespace Data
//
DEBUG ((EFI_D_INFO, " == NVME IDENTIFY NAMESPACE [%d] DATA ==\n", NamespaceId));
DEBUG ((EFI_D_INFO, " NSZE : 0x%x\n", NamespaceData->Nsze));
DEBUG ((EFI_D_INFO, " NCAP : 0x%x\n", NamespaceData->Ncap));
DEBUG ((EFI_D_INFO, " NUSE : 0x%x\n", NamespaceData->Nuse));
DEBUG ((EFI_D_INFO, " LBAF0.LBADS : 0x%x\n", (NamespaceData->LbaFormat[0].Lbads)));
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY NAMESPACE [%d] DATA ==\n", NamespaceId));
DEBUG ((DEBUG_INFO, " NSZE : 0x%x\n", NamespaceData->Nsze));
DEBUG ((DEBUG_INFO, " NCAP : 0x%x\n", NamespaceData->Ncap));
DEBUG ((DEBUG_INFO, " NUSE : 0x%x\n", NamespaceData->Nuse));
DEBUG ((DEBUG_INFO, " LBAF0.LBADS : 0x%x\n", (NamespaceData->LbaFormat[0].Lbads)));
//
// Build controller name for Component Name (2) protocol.
@@ -906,7 +906,7 @@ NvmExpressDriverBindingStart (
UINTN Bytes;
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *Passthru;
DEBUG ((EFI_D_INFO, "NvmExpressDriverBindingStart: start\n"));
DEBUG ((DEBUG_INFO, "NvmExpressDriverBindingStart: start\n"));
Private = NULL;
Passthru = NULL;
@@ -944,7 +944,7 @@ NvmExpressDriverBindingStart (
Private = AllocateZeroPool (sizeof (NVME_CONTROLLER_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((EFI_D_ERROR, "NvmExpressDriverBindingStart: allocating pool for Nvme Private Data failed!\n"));
DEBUG ((DEBUG_ERROR, "NvmExpressDriverBindingStart: allocating pool for Nvme Private Data failed!\n"));
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
}
@@ -1084,7 +1084,7 @@ NvmExpressDriverBindingStart (
}
}
DEBUG ((EFI_D_INFO, "NvmExpressDriverBindingStart: end successfully\n"));
DEBUG ((DEBUG_INFO, "NvmExpressDriverBindingStart: end successfully\n"));
return EFI_SUCCESS;
Exit:
@@ -1122,7 +1122,7 @@ Exit:
Controller
);
DEBUG ((EFI_D_INFO, "NvmExpressDriverBindingStart: end with %r\n", Status));
DEBUG ((DEBUG_INFO, "NvmExpressDriverBindingStart: end with %r\n", Status));
return Status;
}

74
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
View File

@@ -128,13 +128,13 @@ WriteNvmeControllerConfiguration (
return Status;
}
DEBUG ((EFI_D_INFO, "Cc.En: %d\n", Cc->En));
DEBUG ((EFI_D_INFO, "Cc.Css: %d\n", Cc->Css));
DEBUG ((EFI_D_INFO, "Cc.Mps: %d\n", Cc->Mps));
DEBUG ((EFI_D_INFO, "Cc.Ams: %d\n", Cc->Ams));
DEBUG ((EFI_D_INFO, "Cc.Shn: %d\n", Cc->Shn));
DEBUG ((EFI_D_INFO, "Cc.Iosqes: %d\n", Cc->Iosqes));
DEBUG ((EFI_D_INFO, "Cc.Iocqes: %d\n", Cc->Iocqes));
DEBUG ((DEBUG_INFO, "Cc.En: %d\n", Cc->En));
DEBUG ((DEBUG_INFO, "Cc.Css: %d\n", Cc->Css));
DEBUG ((DEBUG_INFO, "Cc.Mps: %d\n", Cc->Mps));
DEBUG ((DEBUG_INFO, "Cc.Ams: %d\n", Cc->Ams));
DEBUG ((DEBUG_INFO, "Cc.Shn: %d\n", Cc->Shn));
DEBUG ((DEBUG_INFO, "Cc.Iosqes: %d\n", Cc->Iosqes));
DEBUG ((DEBUG_INFO, "Cc.Iocqes: %d\n", Cc->Iocqes));
return EFI_SUCCESS;
}
@@ -214,8 +214,8 @@ WriteNvmeAdminQueueAttributes (
return Status;
}
DEBUG ((EFI_D_INFO, "Aqa.Asqs: %d\n", Aqa->Asqs));
DEBUG ((EFI_D_INFO, "Aqa.Acqs: %d\n", Aqa->Acqs));
DEBUG ((DEBUG_INFO, "Aqa.Asqs: %d\n", Aqa->Asqs));
DEBUG ((DEBUG_INFO, "Aqa.Acqs: %d\n", Aqa->Acqs));
return EFI_SUCCESS;
}
@@ -257,7 +257,7 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
return Status;
}
DEBUG ((EFI_D_INFO, "Asq: %lx\n", *Asq));
DEBUG ((DEBUG_INFO, "Asq: %lx\n", *Asq));
return EFI_SUCCESS;
}
@@ -300,7 +300,7 @@ WriteNvmeAdminCompletionQueueBaseAddress (
return Status;
}
DEBUG ((EFI_D_INFO, "Acq: %lxh\n", *Acq));
DEBUG ((DEBUG_INFO, "Acq: %lxh\n", *Acq));
return EFI_SUCCESS;
}
@@ -379,7 +379,7 @@ NvmeDisableController (
);
}
DEBUG ((EFI_D_INFO, "NVMe controller is disabled with status [%r].\n", Status));
DEBUG ((DEBUG_INFO, "NVMe controller is disabled with status [%r].\n", Status));
return Status;
}
@@ -453,7 +453,7 @@ NvmeEnableController (
);
}
DEBUG ((EFI_D_INFO, "NVMe controller is enabled with status [%r].\n", Status));
DEBUG ((DEBUG_INFO, "NVMe controller is enabled with status [%r].\n", Status));
return Status;
}
@@ -764,7 +764,7 @@ NvmeControllerInit (
}
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_INFO, "NvmeControllerInit: failed to enable controller\n"));
DEBUG ((DEBUG_INFO, "NvmeControllerInit: failed to enable controller\n"));
return Status;
}
@@ -778,7 +778,7 @@ NvmeControllerInit (
NULL
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));
DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));
}
//
@@ -790,7 +790,7 @@ NvmeControllerInit (
}
if (Private->Cap.Css != 0x01) {
DEBUG ((EFI_D_INFO, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));
DEBUG ((DEBUG_INFO, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));
return EFI_UNSUPPORTED;
}
@@ -854,15 +854,15 @@ NvmeControllerInit (
Private->CqBuffer[2] = (NVME_CQ *)(UINTN)(Private->Buffer + 5 * EFI_PAGE_SIZE);
Private->CqBufferPciAddr[2] = (NVME_CQ *)(UINTN)(Private->BufferPciAddr + 5 * EFI_PAGE_SIZE);
DEBUG ((EFI_D_INFO, "Private->Buffer = [%016X]\n", (UINT64)(UINTN)Private->Buffer));
DEBUG ((EFI_D_INFO, "Admin Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));
DEBUG ((EFI_D_INFO, "Admin Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));
DEBUG ((EFI_D_INFO, "Admin Submission Queue (SqBuffer[0]) = [%016X]\n", Private->SqBuffer[0]));
DEBUG ((EFI_D_INFO, "Admin Completion Queue (CqBuffer[0]) = [%016X]\n", Private->CqBuffer[0]));
DEBUG ((EFI_D_INFO, "Sync I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private->SqBuffer[1]));
DEBUG ((EFI_D_INFO, "Sync I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private->CqBuffer[1]));
DEBUG ((EFI_D_INFO, "Async I/O Submission Queue (SqBuffer[2]) = [%016X]\n", Private->SqBuffer[2]));
DEBUG ((EFI_D_INFO, "Async I/O Completion Queue (CqBuffer[2]) = [%016X]\n", Private->CqBuffer[2]));
DEBUG ((DEBUG_INFO, "Private->Buffer = [%016X]\n", (UINT64)(UINTN)Private->Buffer));
DEBUG ((DEBUG_INFO, "Admin Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));
DEBUG ((DEBUG_INFO, "Admin Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));
DEBUG ((DEBUG_INFO, "Admin Submission Queue (SqBuffer[0]) = [%016X]\n", Private->SqBuffer[0]));
DEBUG ((DEBUG_INFO, "Admin Completion Queue (CqBuffer[0]) = [%016X]\n", Private->CqBuffer[0]));
DEBUG ((DEBUG_INFO, "Sync I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private->SqBuffer[1]));
DEBUG ((DEBUG_INFO, "Sync I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private->CqBuffer[1]));
DEBUG ((DEBUG_INFO, "Async I/O Submission Queue (SqBuffer[2]) = [%016X]\n", Private->SqBuffer[2]));
DEBUG ((DEBUG_INFO, "Async I/O Completion Queue (CqBuffer[2]) = [%016X]\n", Private->CqBuffer[2]));
//
// Program admin queue attributes.
@@ -925,20 +925,20 @@ NvmeControllerInit (
Sn[20] = 0;
CopyMem (Mn, Private->ControllerData->Mn, sizeof (Private->ControllerData->Mn));
Mn[40] = 0;
DEBUG ((EFI_D_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((EFI_D_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
DEBUG ((EFI_D_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
DEBUG ((EFI_D_INFO, " SN : %a\n", Sn));
DEBUG ((EFI_D_INFO, " MN : %a\n", Mn));
DEBUG ((EFI_D_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64*)(Private->ControllerData->Tnvmcap + 8))));
DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64*)Private->ControllerData->Tnvmcap)));
DEBUG ((EFI_D_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
DEBUG ((EFI_D_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
DEBUG ((EFI_D_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
DEBUG ((EFI_D_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
DEBUG ((EFI_D_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
DEBUG ((EFI_D_INFO, " NN : 0x%x\n", Private->ControllerData->Nn));
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
DEBUG ((DEBUG_INFO, " NN : 0x%x\n", Private->ControllerData->Nn));
//
// Create two I/O completion queues.

107
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
View File

@@ -21,80 +21,80 @@ NvmeDumpStatus (
IN NVME_CQ *Cq
)
{
DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
DEBUG ((DEBUG_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
DEBUG ((DEBUG_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));
DEBUG ((DEBUG_VERBOSE, " NVMe Cmd Execution Result - "));
switch (Cq->Sct) {
case 0x0:
switch (Cq->Sc) {
case 0x0:
DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));
DEBUG ((DEBUG_VERBOSE, "Successful Completion\n"));
break;
case 0x1:
DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Command Opcode\n"));
break;
case 0x2:
DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Field in Command\n"));
break;
case 0x3:
DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));
DEBUG ((DEBUG_VERBOSE, "Command ID Conflict\n"));
break;
case 0x4:
DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));
DEBUG ((DEBUG_VERBOSE, "Data Transfer Error\n"));
break;
case 0x5:
DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
DEBUG ((DEBUG_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
break;
case 0x6:
DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));
DEBUG ((DEBUG_VERBOSE, "Internal Device Error\n"));
break;
case 0x7:
DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));
DEBUG ((DEBUG_VERBOSE, "Command Abort Requested\n"));
break;
case 0x8:
DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));
DEBUG ((DEBUG_VERBOSE, "Command Aborted due to SQ Deletion\n"));
break;
case 0x9:
DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
DEBUG ((DEBUG_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
break;
case 0xA:
DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
DEBUG ((DEBUG_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
break;
case 0xB:
DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Namespace or Format\n"));
break;
case 0xC:
DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));
DEBUG ((DEBUG_VERBOSE, "Command Sequence Error\n"));
break;
case 0xD:
DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
break;
case 0xE:
DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Number of SGL Descriptors\n"));
break;
case 0xF:
DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));
DEBUG ((DEBUG_VERBOSE, "Data SGL Length Invalid\n"));
break;
case 0x10:
DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));
DEBUG ((DEBUG_VERBOSE, "Metadata SGL Length Invalid\n"));
break;
case 0x11:
DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));
DEBUG ((DEBUG_VERBOSE, "SGL Descriptor Type Invalid\n"));
break;
case 0x80:
DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));
DEBUG ((DEBUG_VERBOSE, "LBA Out of Range\n"));
break;
case 0x81:
DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));
DEBUG ((DEBUG_VERBOSE, "Capacity Exceeded\n"));
break;
case 0x82:
DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));
DEBUG ((DEBUG_VERBOSE, "Namespace Not Ready\n"));
break;
case 0x83:
DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));
DEBUG ((DEBUG_VERBOSE, "Reservation Conflict\n"));
break;
}
break;
@@ -102,61 +102,61 @@ NvmeDumpStatus (
case 0x1:
switch (Cq->Sc) {
case 0x0:
DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));
DEBUG ((DEBUG_VERBOSE, "Completion Queue Invalid\n"));
break;
case 0x1:
DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Queue Identifier\n"));
break;
case 0x2:
DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));
DEBUG ((DEBUG_VERBOSE, "Maximum Queue Size Exceeded\n"));
break;
case 0x3:
DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));
DEBUG ((DEBUG_VERBOSE, "Abort Command Limit Exceeded\n"));
break;
case 0x5:
DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
DEBUG ((DEBUG_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
break;
case 0x6:
DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Firmware Slot\n"));
break;
case 0x7:
DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Firmware Image\n"));
break;
case 0x8:
DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Interrupt Vector\n"));
break;
case 0x9:
DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Log Page\n"));
break;
case 0xA:
DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Format\n"));
break;
case 0xB:
DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
DEBUG ((DEBUG_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
break;
case 0xC:
DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Queue Deletion\n"));
break;
case 0xD:
DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));
DEBUG ((DEBUG_VERBOSE, "Feature Identifier Not Saveable\n"));
break;
case 0xE:
DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));
DEBUG ((DEBUG_VERBOSE, "Feature Not Changeable\n"));
break;
case 0xF:
DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));
DEBUG ((DEBUG_VERBOSE, "Feature Not Namespace Specific\n"));
break;
case 0x10:
DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
DEBUG ((DEBUG_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
break;
case 0x80:
DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));
DEBUG ((DEBUG_VERBOSE, "Conflicting Attributes\n"));
break;
case 0x81:
DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));
DEBUG ((DEBUG_VERBOSE, "Invalid Protection Information\n"));
break;
case 0x82:
DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));
DEBUG ((DEBUG_VERBOSE, "Attempted Write to Read Only Range\n"));
break;
}
break;
@@ -164,25 +164,25 @@ NvmeDumpStatus (
case 0x2:
switch (Cq->Sc) {
case 0x80:
DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));
DEBUG ((DEBUG_VERBOSE, "Write Fault\n"));
break;
case 0x81:
DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));
DEBUG ((DEBUG_VERBOSE, "Unrecovered Read Error\n"));
break;
case 0x82:
DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));
DEBUG ((DEBUG_VERBOSE, "End-to-end Guard Check Error\n"));
break;
case 0x83:
DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));
DEBUG ((DEBUG_VERBOSE, "End-to-end Application Tag Check Error\n"));
break;
case 0x84:
DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));
DEBUG ((DEBUG_VERBOSE, "End-to-end Reference Tag Check Error\n"));
break;
case 0x85:
DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));
DEBUG ((DEBUG_VERBOSE, "Compare Failure\n"));
break;
case 0x86:
DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));
DEBUG ((DEBUG_VERBOSE, "Access Denied\n"));
break;
}
break;
@@ -268,7 +268,7 @@ NvmeCreatePrpList (
);
if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {
DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
DEBUG ((DEBUG_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
goto EXIT;
}
//
@@ -578,7 +578,7 @@ NvmExpressPassThru (
//
ASSERT (Sq->Psdt == 0);
if (Sq->Psdt != 0) {
DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
DEBUG ((DEBUG_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
return EFI_UNSUPPORTED;
}
@@ -1182,4 +1182,3 @@ Exit:
return Status;
}

3
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
View File

@@ -1003,7 +1003,7 @@ PciHostBridgeAdjustAllocation (
Status = RejectPciDevice (PciResNode->PciDev);
if (Status == EFI_SUCCESS) {
DEBUG ((
EFI_D_ERROR,
DEBUG_ERROR,
"PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber
));
@@ -2207,4 +2207,3 @@ AddHostBridgeEnumerator (
return EFI_SUCCESS;
}

23
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

@@ -231,7 +231,7 @@ PciSearchDevice (
PciIoDevice = NULL;
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
"PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
IS_PCI_BRIDGE (Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :
@@ -398,7 +398,7 @@ DumpPpbPaddingResource (
if ((Type != PciBarTypeUnknown) && ((ResourceType == PciBarTypeUnknown) || (ResourceType == Type))) {
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
" Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLen
));
@@ -425,7 +425,7 @@ DumpPciBars (
}
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
" BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset
@@ -438,13 +438,13 @@ DumpPciBars (
}
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
" VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
));
}
DEBUG ((EFI_D_INFO, "\n"));
DEBUG ((DEBUG_INFO, "\n"));
}
/**
@@ -1903,7 +1903,7 @@ PciParseBar (
// Fix the length to support some special 64 bit BAR
//
if (Value == 0) {
DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
Value = (UINT32) -1;
} else {
Value |= ((UINT32)(-1) << HighBitSet32 (Value));
@@ -2282,7 +2282,7 @@ CreatePciIoDevice (
&Data32
);
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
" ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
Bridge->BusNumber,
Bridge->DeviceNumber,
@@ -2291,7 +2291,7 @@ CreatePciIoDevice (
}
}
DEBUG ((EFI_D_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice->AriCapabilityOffset));
DEBUG ((DEBUG_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice->AriCapabilityOffset));
}
}
@@ -2401,12 +2401,12 @@ CreatePciIoDevice (
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
" SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset
));
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
" InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice->SrIovCapabilityOffset
));
@@ -2421,7 +2421,7 @@ CreatePciIoDevice (
NULL
);
if (!EFI_ERROR (Status)) {
DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
}
}
@@ -2869,4 +2869,3 @@ ResetAllPpbBusNumber (
}
}
}

36
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

@@ -215,7 +215,7 @@ DumpBridgeResource (
if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
DEBUG ((
EFI_D_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
DEBUG_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
BridgeResource->Length, BridgeResource->Alignment
@@ -228,7 +228,7 @@ DumpBridgeResource (
if (Resource->ResourceUsage == PciResUsageTypical) {
Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
DEBUG ((
EFI_D_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s [%02x|%02x|%02x:",
DEBUG_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s [%02x|%02x|%02x:",
Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :
@@ -244,20 +244,20 @@ DumpBridgeResource (
//
// The resource requirement comes from the device itself.
//
DEBUG ((EFI_D_INFO, "%02x]", Bar[Resource->Bar].Offset));
DEBUG ((DEBUG_INFO, "%02x]", Bar[Resource->Bar].Offset));
} else {
//
// The resource requirement comes from the subordinate devices.
//
DEBUG ((EFI_D_INFO, "**]"));
DEBUG ((DEBUG_INFO, "**]"));
}
} else {
DEBUG ((EFI_D_INFO, " Base = Padding;\tLength = 0x%lx;\tAlignment = 0x%lx", Resource->Length, Resource->Alignment));
DEBUG ((DEBUG_INFO, " Base = Padding;\tLength = 0x%lx;\tAlignment = 0x%lx", Resource->Length, Resource->Alignment));
}
if (BridgeResource->ResType != Resource->ResType) {
DEBUG ((EFI_D_INFO, "; Type = %s", mBarTypeStr[MIN (Resource->ResType, PciBarTypeMaxType)]));
DEBUG ((DEBUG_INFO, "; Type = %s", mBarTypeStr[MIN (Resource->ResType, PciBarTypeMaxType)]));
}
DEBUG ((EFI_D_INFO, "\n"));
DEBUG ((DEBUG_INFO, "\n"));
}
}
}
@@ -321,7 +321,7 @@ DumpResourceMap (
PCI_RESOURCE_NODE **ChildResources;
UINTN ChildResourceCount;
DEBUG ((EFI_D_INFO, "PciBus: Resource Map for "));
DEBUG ((DEBUG_INFO, "PciBus: Resource Map for "));
Status = gBS->OpenProtocol (
Bridge->Handle,
@@ -333,7 +333,7 @@ DumpResourceMap (
);
if (EFI_ERROR (Status)) {
DEBUG ((
EFI_D_INFO, "Bridge [%02x|%02x|%02x]\n",
DEBUG_INFO, "Bridge [%02x|%02x|%02x]\n",
Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber
));
} else {
@@ -342,7 +342,7 @@ DumpResourceMap (
FALSE,
FALSE
);
DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
DEBUG ((DEBUG_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
if (Str != NULL) {
FreePool (Str);
}
@@ -351,7 +351,7 @@ DumpResourceMap (
for (Index = 0; Index < ResourceCount; Index++) {
DumpBridgeResource (Resources[Index]);
}
DEBUG ((EFI_D_INFO, "\n"));
DEBUG ((DEBUG_INFO, "\n"));
for ( Link = Bridge->ChildList.ForwardLink
; Link != &Bridge->ChildList
@@ -622,7 +622,7 @@ PciHostBridgeResourceAllocator (
// If SubmitResources returns error, PciBus isn't able to start.
// It's a fatal error so assertion is added.
//
DEBUG ((EFI_D_INFO, "PciBus: HostBridge->SubmitResources() - %r\n", Status));
DEBUG ((DEBUG_INFO, "PciBus: HostBridge->SubmitResources() - %r\n", Status));
ASSERT_EFI_ERROR (Status);
}
@@ -654,7 +654,7 @@ PciHostBridgeResourceAllocator (
// Notify platform to start to program the resource
//
Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);
DEBUG ((EFI_D_INFO, "PciBus: HostBridge->NotifyPhase(AllocateResources) - %r\n", Status));
DEBUG ((DEBUG_INFO, "PciBus: HostBridge->NotifyPhase(AllocateResources) - %r\n", Status));
if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
//
// If Hot Plug is not supported
@@ -1340,9 +1340,9 @@ PciScanBus (
TempReservedBusNum = PciDevice->ReservedBusNum;
if (Func == 0) {
DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x\n", *SubBusNumber));
DEBUG ((DEBUG_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x\n", *SubBusNumber));
} else {
DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x (Update)\n", *SubBusNumber));
DEBUG ((DEBUG_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x (Update)\n", *SubBusNumber));
}
}
}
@@ -1522,7 +1522,7 @@ PciHostBridgeEnumerator (
return Status;
}
DEBUG((EFI_D_INFO, "PCI Bus First Scanning\n"));
DEBUG((DEBUG_INFO, "PCI Bus First Scanning\n"));
RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
@@ -1601,7 +1601,7 @@ PciHostBridgeEnumerator (
Status = AllRootHPCInitialized (STALL_1_SECOND * 15);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Some root HPC failed to initialize\n"));
DEBUG ((DEBUG_ERROR, "Some root HPC failed to initialize\n"));
return Status;
}
@@ -1614,7 +1614,7 @@ PciHostBridgeEnumerator (
return Status;
}
DEBUG((EFI_D_INFO, "PCI Bus Second Scanning\n"));
DEBUG((DEBUG_INFO, "PCI Bus Second Scanning\n"));
RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {

22
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
View File

@@ -119,13 +119,13 @@ IntersectIoDescriptor (
Status = gDS->AddIoSpace (EfiGcdIoTypeIo, IntersectionBase,
IntersectionEnd - IntersectionBase);
DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE,
DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
"%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
IntersectionBase, IntersectionEnd, Status));
return Status;
}
DEBUG ((EFI_D_ERROR, "%a: %a: desc [%Lx, %Lx) type %u conflicts with "
DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u conflicts with "
"aperture [%Lx, %Lx)\n", gEfiCallerBaseName, __FUNCTION__,
Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
(UINT32)Descriptor->GcdIoType, Base, Base + Length));
@@ -155,7 +155,7 @@ AddIoSpace (
Status = gDS->GetIoSpaceMap (&NumberOfDescriptors, &IoSpaceMap);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "%a: %a: GetIoSpaceMap(): %r\n",
DEBUG ((DEBUG_ERROR, "%a: %a: GetIoSpaceMap(): %r\n",
gEfiCallerBaseName, __FUNCTION__, Status));
return Status;
}
@@ -263,13 +263,13 @@ IntersectMemoryDescriptor (
IntersectionBase, IntersectionEnd - IntersectionBase,
Capabilities);
DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE,
DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
"%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
IntersectionBase, IntersectionEnd, Status));
return Status;
}
DEBUG ((EFI_D_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
"with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,
Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
(UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,
@@ -302,7 +302,7 @@ AddMemoryMappedIoSpace (
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
gEfiCallerBaseName, __FUNCTION__, Status));
return Status;
}
@@ -828,7 +828,7 @@ NotifyPhase (
}
}
DEBUG ((EFI_D_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));
DEBUG ((DEBUG_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));
for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
@@ -838,7 +838,7 @@ NotifyPhase (
}
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
DEBUG ((EFI_D_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));
DEBUG ((DEBUG_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));
for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {
if (RootBridge->ResAllocNode[Index1].Status == ResNone) {
@@ -1360,7 +1360,7 @@ SubmitResources (
) {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
DEBUG ((EFI_D_INFO, "PciHostBridge: SubmitResources for %s\n", RootBridge->DevicePathStr));
DEBUG ((DEBUG_INFO, "PciHostBridge: SubmitResources for %s\n", RootBridge->DevicePathStr));
//
// Check the resource descriptors.
// If the Configuration includes one or more invalid resource descriptors, all the resource
@@ -1371,11 +1371,11 @@ SubmitResources (
return EFI_INVALID_PARAMETER;
}
DEBUG ((EFI_D_INFO, " %s: Granularity/SpecificFlag = %ld / %02x%s\n",
DEBUG ((DEBUG_INFO, " %s: Granularity/SpecificFlag = %ld / %02x%s\n",
mAcpiAddressSpaceTypeStr[Descriptor->ResType], Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
(Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0 ? L" (Prefetchable)" : L""
));
DEBUG ((EFI_D_INFO, " Length/Alignment = 0x%lx / 0x%lx\n", Descriptor->AddrLen, Descriptor->AddrRangeMax));
DEBUG ((DEBUG_INFO, " Length/Alignment = 0x%lx / 0x%lx\n", Descriptor->AddrLen, Descriptor->AddrRangeMax));
switch (Descriptor->ResType) {
case ACPI_ADDRESS_SPACE_TYPE_MEM:
if (Descriptor->AddrSpaceGranularity != 32 && Descriptor->AddrSpaceGranularity != 64) {

14
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
View File

@@ -71,17 +71,17 @@ CreateRootBridge (
DevicePathStr = NULL;
DEBUG ((EFI_D_INFO, "RootBridge: "));
DEBUG ((EFI_D_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));
DEBUG ((EFI_D_INFO, " Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
DEBUG ((EFI_D_INFO, " DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
DEBUG ((EFI_D_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
DEBUG ((EFI_D_INFO, " AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,
DEBUG ((DEBUG_INFO, "RootBridge: "));
DEBUG ((DEBUG_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));
DEBUG ((DEBUG_INFO, " Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
DEBUG ((DEBUG_INFO, " DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
DEBUG ((DEBUG_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
DEBUG ((DEBUG_INFO, " AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,
(Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
(Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
));
DEBUG ((
EFI_D_INFO, " Bus: %lx - %lx Translation=%lx\n",
DEBUG_INFO, " Bus: %lx - %lx Translation=%lx\n",
Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation
));
//

6
MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c
View File

@@ -943,7 +943,7 @@ SerialControllerDriverStart (
Node = NextDevicePathNode (Node);
} while (!IsDevicePathEnd (Node));
Status = CreateSerialDevice (Controller, Uart, ParentDevicePath, FALSE, Acpi->UID, ParentIo, NULL, NULL);
DEBUG ((EFI_D_INFO, "PciSioSerial: Create SIO child serial device - %r\n", Status));
DEBUG ((DEBUG_INFO, "PciSioSerial: Create SIO child serial device - %r\n", Status));
}
} else {
Status = ParentIo.PciIo->Pci.Read (ParentIo.PciIo, EfiPciIoWidthUint8, 0, sizeof (Pci), &Pci);
@@ -1024,7 +1024,7 @@ SerialControllerDriverStart (
}
Status = CreateSerialDevice (Controller, Uart, ParentDevicePath, FALSE, 0, ParentIo, PciSerialParameter, PciDeviceInfo);
DEBUG ((EFI_D_INFO, "PciSioSerial: Create PCI child serial device (single) - %r\n", Status));
DEBUG ((DEBUG_INFO, "PciSioSerial: Create PCI child serial device (single) - %r\n", Status));
if (!EFI_ERROR (Status)) {
PciDeviceInfo->ChildCount++;
}
@@ -1045,7 +1045,7 @@ SerialControllerDriverStart (
//
Status = CreateSerialDevice (Controller, Uart, ParentDevicePath, TRUE, PciSerialCount, ParentIo, PciSerialParameter, PciDeviceInfo);
PciSerialCount++;
DEBUG ((EFI_D_INFO, "PciSioSerial: Create PCI child serial device (multiple) - %r\n", Status));
DEBUG ((DEBUG_INFO, "PciSioSerial: Create PCI child serial device (multiple) - %r\n", Status));
if (!EFI_ERROR (Status)) {
PciDeviceInfo->ChildCount++;
}

12
MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
View File

@@ -134,9 +134,9 @@ VerifyUartParameters (
}
Percent = DivU64x32 (MultU64x32 (BaudRate, 100), ComputedBaudRate);
DEBUG ((EFI_D_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((EFI_D_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((EFI_D_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((DEBUG_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
//
// If the requested BaudRate is not supported:
@@ -176,9 +176,9 @@ VerifyUartParameters (
return FALSE;
}
DEBUG ((EFI_D_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((EFI_D_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((EFI_D_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((DEBUG_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
if (ActualBaudRate != NULL) {
*ActualBaudRate = ComputedBaudRate;

21
MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c
View File

@@ -89,7 +89,7 @@ CalculateBestPioMode (
if ((IdentifyData->AtaData.field_validity & 0x02) == 0x02) {
AdvancedPioMode = IdentifyData->AtaData.advanced_pio_modes;
DEBUG ((EFI_D_INFO, "CalculateBestPioMode: AdvancedPioMode = %x\n", AdvancedPioMode));
DEBUG ((DEBUG_INFO, "CalculateBestPioMode: AdvancedPioMode = %x\n", AdvancedPioMode));
for (Index = 0; Index < 8; Index++) {
if ((AdvancedPioMode & 0x01) != 0) {
@@ -203,7 +203,7 @@ CalculateBestUdmaMode (
}
DeviceUDmaMode = IdentifyData->AtaData.ultra_dma_mode;
DEBUG ((EFI_D_INFO, "CalculateBestUdmaMode: DeviceUDmaMode = %x\n", DeviceUDmaMode));
DEBUG ((DEBUG_INFO, "CalculateBestUdmaMode: DeviceUDmaMode = %x\n", DeviceUDmaMode));
DeviceUDmaMode &= 0x3f;
TempMode = 0; // initialize it to UDMA-0
@@ -362,7 +362,7 @@ SataControllerStart (
UINT64 Supports;
UINT8 MaxPortNumber;
DEBUG ((EFI_D_INFO, "SataControllerStart start\n"));
DEBUG ((DEBUG_INFO, "SataControllerStart start\n"));
Private = NULL;
@@ -378,7 +378,7 @@ SataControllerStart (
EFI_OPEN_PROTOCOL_BY_DRIVER
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "SataControllerStart error. return status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "SataControllerStart error. return status = %r\n", Status));
return Status;
}
@@ -419,7 +419,7 @@ SataControllerStart (
}
DEBUG ((
EFI_D_INFO,
DEBUG_INFO,
"Original PCI Attributes = 0x%llx\n",
Private->OriginalPciAttributes
));
@@ -434,7 +434,7 @@ SataControllerStart (
goto Done;
}
DEBUG ((EFI_D_INFO, "Supported PCI Attributes = 0x%llx\n", Supports));
DEBUG ((DEBUG_INFO, "Supported PCI Attributes = 0x%llx\n", Supports));
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
Status = PciIo->Attributes (
@@ -447,7 +447,7 @@ SataControllerStart (
goto Done;
}
DEBUG ((EFI_D_INFO, "Enabled PCI Attributes = 0x%llx\n", Supports));
DEBUG ((DEBUG_INFO, "Enabled PCI Attributes = 0x%llx\n", Supports));
Private->PciAttributesChanged = TRUE;
Status = PciIo->Pci.Read (
@@ -561,7 +561,7 @@ Done:
}
}
DEBUG ((EFI_D_INFO, "SataControllerStart end with %r\n", Status));
DEBUG ((DEBUG_INFO, "SataControllerStart end with %r\n", Status));
return Status;
}
@@ -1048,7 +1048,7 @@ IdeInitCalculateMode (
} else {
(*SupportedModes)->PioMode.Valid = FALSE;
}
DEBUG ((EFI_D_INFO, "IdeInitCalculateMode: PioMode = %x\n", (*SupportedModes)->PioMode.Mode));
DEBUG ((DEBUG_INFO, "IdeInitCalculateMode: PioMode = %x\n", (*SupportedModes)->PioMode.Mode));
Status = CalculateBestUdmaMode (
IdentifyData,
@@ -1063,7 +1063,7 @@ IdeInitCalculateMode (
} else {
(*SupportedModes)->UdmaMode.Valid = FALSE;
}
DEBUG ((EFI_D_INFO, "IdeInitCalculateMode: UdmaMode = %x\n", (*SupportedModes)->UdmaMode.Mode));
DEBUG ((DEBUG_INFO, "IdeInitCalculateMode: UdmaMode = %x\n", (*SupportedModes)->UdmaMode.Mode));
//
// The modes other than PIO and UDMA are not supported
@@ -1105,4 +1105,3 @@ IdeInitSetTiming (
{
return EFI_SUCCESS;
}

2
MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c
View File

@@ -108,7 +108,7 @@ InitializeSdMmcHcPeim (
Private = (SD_MMC_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((EFI_D_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));
DEBUG ((DEBUG_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));
return EFI_OUT_OF_RESOURCES;
}

2
MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
View File

@@ -99,7 +99,7 @@ InitializeUfsHcPeim (
Private = (UFS_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (UFS_HC_PEI_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((EFI_D_ERROR, "Failed to allocate memory for UFS_HC_PEI_PRIVATE_DATA! \n"));
DEBUG ((DEBUG_ERROR, "Failed to allocate memory for UFS_HC_PEI_PRIVATE_DATA! \n"));
return EFI_OUT_OF_RESOURCES;
}

5
MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
View File

@@ -323,7 +323,7 @@ Uhci2GetCapability (
Uhc->RootPorts = *PortNumber;
DEBUG ((EFI_D_INFO, "Uhci2GetCapability: %d ports\n", (UINT32)Uhc->RootPorts));
DEBUG ((DEBUG_INFO, "Uhci2GetCapability: %d ports\n", (UINT32)Uhc->RootPorts));
return EFI_SUCCESS;
}
@@ -378,7 +378,7 @@ Uhci2GetRootHubPortStatus (
}
if ((PortSC & USBPORTSC_SUSP) != 0) {
DEBUG ((EFI_D_INFO, "Uhci2GetRootHubPortStatus: port %d is suspended\n", PortNumber));
DEBUG ((DEBUG_INFO, "Uhci2GetRootHubPortStatus: port %d is suspended\n", PortNumber));
PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;
}
@@ -1880,4 +1880,3 @@ UhciDriverBindingStop (
return EFI_SUCCESS;
}

51
MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.c
View File

@@ -20,12 +20,12 @@ UhciDumpQh (
IN UHCI_QH_SW *QhSw
)
{
DEBUG ((EFI_D_VERBOSE, "&QhSw @ 0x%p\n", QhSw));
DEBUG ((EFI_D_VERBOSE, "QhSw.NextQh - 0x%p\n", QhSw->NextQh));
DEBUG ((EFI_D_VERBOSE, "QhSw.TDs - 0x%p\n", QhSw->TDs));
DEBUG ((EFI_D_VERBOSE, "QhSw.QhHw:\n"));
DEBUG ((EFI_D_VERBOSE, " Horizon Link - %x\n", QhSw->QhHw.HorizonLink));
DEBUG ((EFI_D_VERBOSE, " Vertical Link - %x\n\n", QhSw->QhHw.VerticalLink));
DEBUG ((DEBUG_VERBOSE, "&QhSw @ 0x%p\n", QhSw));
DEBUG ((DEBUG_VERBOSE, "QhSw.NextQh - 0x%p\n", QhSw->NextQh));
DEBUG ((DEBUG_VERBOSE, "QhSw.TDs - 0x%p\n", QhSw->TDs));
DEBUG ((DEBUG_VERBOSE, "QhSw.QhHw:\n"));
DEBUG ((DEBUG_VERBOSE, " Horizon Link - %x\n", QhSw->QhHw.HorizonLink));
DEBUG ((DEBUG_VERBOSE, " Vertical Link - %x\n\n", QhSw->QhHw.VerticalLink));
}
@@ -45,27 +45,26 @@ UhciDumpTds (
CurTdSw = TdSw;
while (CurTdSw != NULL) {
DEBUG ((EFI_D_VERBOSE, "TdSw @ 0x%p\n", CurTdSw));
DEBUG ((EFI_D_VERBOSE, "TdSw.NextTd - 0x%p\n", CurTdSw->NextTd));
DEBUG ((EFI_D_VERBOSE, "TdSw.DataLen - %d\n", CurTdSw->DataLen));
DEBUG ((EFI_D_VERBOSE, "TdSw.Data - 0x%p\n", CurTdSw->Data));
DEBUG ((EFI_D_VERBOSE, "TdHw:\n"));
DEBUG ((EFI_D_VERBOSE, " NextLink - 0x%x\n", CurTdSw->TdHw.NextLink));
DEBUG ((EFI_D_VERBOSE, " ActualLen - %d\n", CurTdSw->TdHw.ActualLen));
DEBUG ((EFI_D_VERBOSE, " Status - 0x%x\n", CurTdSw->TdHw.Status));
DEBUG ((EFI_D_VERBOSE, " IOC - %d\n", CurTdSw->TdHw.IntOnCpl));
DEBUG ((EFI_D_VERBOSE, " IsIsoCh - %d\n", CurTdSw->TdHw.IsIsoch));
DEBUG ((EFI_D_VERBOSE, " LowSpeed - %d\n", CurTdSw->TdHw.LowSpeed));
DEBUG ((EFI_D_VERBOSE, " ErrorCount - %d\n", CurTdSw->TdHw.ErrorCount));
DEBUG ((EFI_D_VERBOSE, " ShortPacket - %d\n", CurTdSw->TdHw.ShortPacket));
DEBUG ((EFI_D_VERBOSE, " PidCode - 0x%x\n", CurTdSw->TdHw.PidCode));
DEBUG ((EFI_D_VERBOSE, " DevAddr - %d\n", CurTdSw->TdHw.DeviceAddr));
DEBUG ((EFI_D_VERBOSE, " EndPoint - %d\n", CurTdSw->TdHw.EndPoint));
DEBUG ((EFI_D_VERBOSE, " DataToggle - %d\n", CurTdSw->TdHw.DataToggle));
DEBUG ((EFI_D_VERBOSE, " MaxPacketLen - %d\n", CurTdSw->TdHw.MaxPacketLen));
DEBUG ((EFI_D_VERBOSE, " DataBuffer - 0x%x\n\n",CurTdSw->TdHw.DataBuffer));
DEBUG ((DEBUG_VERBOSE, "TdSw @ 0x%p\n", CurTdSw));
DEBUG ((DEBUG_VERBOSE, "TdSw.NextTd - 0x%p\n", CurTdSw->NextTd));
DEBUG ((DEBUG_VERBOSE, "TdSw.DataLen - %d\n", CurTdSw->DataLen));
DEBUG ((DEBUG_VERBOSE, "TdSw.Data - 0x%p\n", CurTdSw->Data));
DEBUG ((DEBUG_VERBOSE, "TdHw:\n"));
DEBUG ((DEBUG_VERBOSE, " NextLink - 0x%x\n", CurTdSw->TdHw.NextLink));
DEBUG ((DEBUG_VERBOSE, " ActualLen - %d\n", CurTdSw->TdHw.ActualLen));
DEBUG ((DEBUG_VERBOSE, " Status - 0x%x\n", CurTdSw->TdHw.Status));
DEBUG ((DEBUG_VERBOSE, " IOC - %d\n", CurTdSw->TdHw.IntOnCpl));
DEBUG ((DEBUG_VERBOSE, " IsIsoCh - %d\n", CurTdSw->TdHw.IsIsoch));
DEBUG ((DEBUG_VERBOSE, " LowSpeed - %d\n", CurTdSw->TdHw.LowSpeed));
DEBUG ((DEBUG_VERBOSE, " ErrorCount - %d\n", CurTdSw->TdHw.ErrorCount));
DEBUG ((DEBUG_VERBOSE, " ShortPacket - %d\n", CurTdSw->TdHw.ShortPacket));
DEBUG ((DEBUG_VERBOSE, " PidCode - 0x%x\n", CurTdSw->TdHw.PidCode));
DEBUG ((DEBUG_VERBOSE, " DevAddr - %d\n", CurTdSw->TdHw.DeviceAddr));
DEBUG ((DEBUG_VERBOSE, " EndPoint - %d\n", CurTdSw->TdHw.EndPoint));
DEBUG ((DEBUG_VERBOSE, " DataToggle - %d\n", CurTdSw->TdHw.DataToggle));
DEBUG ((DEBUG_VERBOSE, " MaxPacketLen - %d\n", CurTdSw->TdHw.MaxPacketLen));
DEBUG ((DEBUG_VERBOSE, " DataBuffer - 0x%x\n\n",CurTdSw->TdHw.DataBuffer));
CurTdSw = CurTdSw->NextTd;
}
}

10
MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
View File

@@ -38,7 +38,7 @@ UhciReadReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));
Data = 0xFFFF;
}
@@ -74,7 +74,7 @@ UhciWriteReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));
}
}
@@ -144,7 +144,7 @@ UhciAckAllInterrupt (
// is a temporary error status.
//
if (!UhciIsHcWorking (Uhc->PciIo)) {
DEBUG ((EFI_D_ERROR, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
DEBUG ((DEBUG_ERROR, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
Uhc->Usb2Hc.SetState (&Uhc->Usb2Hc, EfiUsbHcStateOperational);
}
}
@@ -208,7 +208,7 @@ UhciIsHcWorking (
UsbSts = UhciReadReg (PciIo, USBSTS_OFFSET);
if ((UsbSts & (USBSTS_HCPE | USBSTS_HSE | USBSTS_HCH)) != 0) {
DEBUG ((EFI_D_ERROR, "UhciIsHcWorking: current USB state is %x\n", UsbSts));
DEBUG ((DEBUG_ERROR, "UhciIsHcWorking: current USB state is %x\n", UsbSts));
return FALSE;
}
@@ -245,7 +245,7 @@ UhciSetFrameListBaseAddr (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status));
DEBUG ((DEBUG_ERROR, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status));
}
}

4
MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
View File

@@ -600,14 +600,14 @@ UhciExecuteTransfer (
}
if (!Finished) {
DEBUG ((EFI_D_ERROR, "UhciExecuteTransfer: execution not finished for %dms\n", (UINT32)TimeOut));
DEBUG ((DEBUG_ERROR, "UhciExecuteTransfer: execution not finished for %dms\n", (UINT32)TimeOut));
UhciDumpQh (Qh);
UhciDumpTds (Td);
Status = EFI_TIMEOUT;
} else if (QhResult->Result != EFI_USB_NOERROR) {
DEBUG ((EFI_D_ERROR, "UhciExecuteTransfer: execution failed with result %x\n", QhResult->Result));
DEBUG ((DEBUG_ERROR, "UhciExecuteTransfer: execution failed with result %x\n", QhResult->Result));
UhciDumpQh (Qh);
UhciDumpTds (Td);

2
MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.c
View File

@@ -468,7 +468,7 @@ UsbHcAllocateMem (
NewBlock = UsbHcAllocMemBlock (Pool, Pages);
if (NewBlock == NULL) {
DEBUG ((EFI_D_INFO, "UsbHcAllocateMem: failed to allocate block\n"));
DEBUG ((DEBUG_INFO, "UsbHcAllocateMem: failed to allocate block\n"));
return NULL;
}

2
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
View File

@@ -503,7 +503,7 @@ UsbHcAllocateMem (
NewBlock = UsbHcAllocMemBlock (Pool, Pages);
if (NewBlock == NULL) {
DEBUG ((EFI_D_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
DEBUG ((DEBUG_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
return NULL;
}

63
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
View File

@@ -120,7 +120,7 @@ XhcGetCapability (
*MaxSpeed = EFI_USB_SPEED_SUPER;
*PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts);
*Is64BitCapable = (UINT8) Xhc->Support64BitDma;
DEBUG ((EFI_D_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
DEBUG ((DEBUG_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
gBS->RestoreTPL (OldTpl);
@@ -216,7 +216,7 @@ XhcReset (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcReset: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcReset: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -260,7 +260,7 @@ XhcGetState (
*State = EfiUsbHcStateOperational;
}
DEBUG ((EFI_D_INFO, "XhcGetState: current state %d\n", *State));
DEBUG ((DEBUG_INFO, "XhcGetState: current state %d\n", *State));
gBS->RestoreTPL (OldTpl);
return EFI_SUCCESS;
@@ -336,7 +336,7 @@ XhcSetState (
Status = EFI_INVALID_PARAMETER;
}
DEBUG ((EFI_D_INFO, "XhcSetState: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcSetState: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -530,7 +530,7 @@ XhcSetRootHubPortFeature (
break;
case EfiUsbPortReset:
DEBUG ((EFI_D_INFO, "XhcUsbPortReset!\n"));
DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));
//
// Make sure Host Controller not halt before reset it
//
@@ -538,7 +538,7 @@ XhcSetRootHubPortFeature (
Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
break;
}
}
@@ -571,7 +571,7 @@ XhcSetRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -706,7 +706,7 @@ XhcClearRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -914,7 +914,7 @@ XhcControlTransfer (
Len = 0;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcControlTransfer: HC halted at entrance\n"));
DEBUG ((DEBUG_ERROR, "XhcControlTransfer: HC halted at entrance\n"));
goto ON_EXIT;
}
@@ -1043,7 +1043,7 @@ XhcControlTransfer (
// Don't support multi-TT feature for super speed hub now.
//
MTT = 0;
DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
DEBUG ((DEBUG_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
} else {
MTT = 0;
}
@@ -1162,7 +1162,7 @@ XhcControlTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
gBS->RestoreTPL (OldTpl);
@@ -1250,7 +1250,7 @@ XhcBulkTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: HC is halted\n"));
DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: HC is halted\n"));
goto ON_EXIT;
}
@@ -1282,7 +1282,7 @@ XhcBulkTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
gBS->RestoreTPL (OldTpl);
@@ -1386,14 +1386,14 @@ XhcAsyncInterruptTransfer (
}
Status = XhciDelAsyncIntTransfer (Xhc, DeviceAddress, EndPointAddress);
DEBUG ((EFI_D_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));
DEBUG ((DEBUG_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));
goto ON_EXIT;
}
Status = EFI_SUCCESS;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));
DEBUG ((DEBUG_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));
Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
@@ -1508,7 +1508,7 @@ XhcSyncInterruptTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
DEBUG ((DEBUG_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
goto ON_EXIT;
}
@@ -1536,7 +1536,7 @@ XhcSyncInterruptTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
gBS->RestoreTPL (OldTpl);
@@ -1805,14 +1805,14 @@ XhcCreateUsbHc (
Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
//
// Create AsyncRequest Polling Timer
@@ -1972,7 +1972,7 @@ XhcDriverBindingStart (
}
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));
goto CLOSE_PCIIO;
}
@@ -1982,7 +1982,7 @@ XhcDriverBindingStart (
Xhc = XhcCreateUsbHc (PciIo, HcDevicePath, OriginalPciAttributes);
if (Xhc == NULL) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));
return EFI_OUT_OF_RESOURCES;
}
@@ -2000,7 +2000,7 @@ XhcDriverBindingStart (
if (!EFI_ERROR (Status)) {
Xhc->Support64BitDma = TRUE;
} else {
DEBUG ((EFI_D_WARN,
DEBUG ((DEBUG_WARN,
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
__FUNCTION__, Controller, Status));
}
@@ -2032,7 +2032,7 @@ XhcDriverBindingStart (
//
Status = gBS->SetTimer (Xhc->PollTimer, TimerPeriodic, XHC_ASYNC_TIMER_INTERVAL);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));
XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
goto FREE_POOL;
}
@@ -2078,11 +2078,11 @@ XhcDriverBindingStart (
&Xhc->Usb2Hc
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
goto FREE_POOL;
}
DEBUG ((EFI_D_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));
DEBUG ((DEBUG_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));
return EFI_SUCCESS;
FREE_POOL:
@@ -2233,4 +2233,3 @@ XhcDriverBindingStop (
return EFI_SUCCESS;
}

25
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
View File

@@ -38,7 +38,7 @@ XhcReadCapReg8 (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFF;
}
@@ -74,7 +74,7 @@ XhcReadCapReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -112,7 +112,7 @@ XhcReadOpReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -148,7 +148,7 @@ XhcWriteOpReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -185,7 +185,7 @@ XhcWriteDoorBellReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -219,7 +219,7 @@ XhcReadRuntimeReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -255,7 +255,7 @@ XhcWriteRuntimeReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -289,7 +289,7 @@ XhcReadExtCapReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -325,7 +325,7 @@ XhcWriteExtCapReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -508,7 +508,7 @@ XhcSetBiosOwnership (
return;
}
DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
DEBUG ((DEBUG_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);
@@ -532,7 +532,7 @@ XhcClearBiosOwnership (
return;
}
DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
DEBUG ((DEBUG_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);
@@ -666,7 +666,7 @@ XhcResetHC (
Status = EFI_SUCCESS;
DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
DEBUG ((DEBUG_INFO, "XhcResetHC!\n"));
//
// Host can only be reset when it is halt. If not so, halt it
//
@@ -748,4 +748,3 @@ XhcRunHC (
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
return Status;
}

122
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

@@ -82,7 +82,7 @@ XhcCmdTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: HC is halted\n"));
goto ON_EXIT;
}
@@ -92,7 +92,7 @@ XhcCmdTransfer (
Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: failed to create URB\n"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
@@ -172,7 +172,7 @@ XhcCreateUrb (
Status = XhcCreateTransferTrb (Xhc, Urb);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
FreePool (Urb);
Urb = NULL;
}
@@ -269,7 +269,7 @@ XhcCreateTransferTrb (
Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
return EFI_OUT_OF_RESOURCES;
}
@@ -446,7 +446,7 @@ XhcCreateTransferTrb (
break;
default:
DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));
ASSERT (FALSE);
break;
}
@@ -582,7 +582,7 @@ XhcInitSched (
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
DEBUG ((DEBUG_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
//
// Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
@@ -660,14 +660,14 @@ XhcRecoverHaltedEndpoint (
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
//
// 1) Send Reset endpoint command to transit from halt to stop state
//
Status = XhcResetEndpoint(Xhc, SlotId, Dci);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -676,7 +676,7 @@ XhcRecoverHaltedEndpoint (
//
Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -722,14 +722,14 @@ XhcDequeueTrbFromEndpoint (
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
//
// 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
//
Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -1159,25 +1159,25 @@ XhcCheckUrbResult (
case TRB_COMPLETION_STALL_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_STALL;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_BABBLE_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_DATA_BUFFER_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_USB_TRANSACTION_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_STOPPED:
@@ -1193,7 +1193,7 @@ XhcCheckUrbResult (
case TRB_COMPLETION_SHORT_PACKET:
case TRB_COMPLETION_SUCCESS:
if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
DEBUG ((DEBUG_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
}
TRBType = (UINT8) (TRBPtr->Type);
@@ -1206,7 +1206,7 @@ XhcCheckUrbResult (
break;
default:
DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
goto EXIT;
@@ -1396,7 +1396,7 @@ XhciDelAsyncIntTransfer (
//
Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
DEBUG ((DEBUG_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
}
RemoveEntryList (&Urb->UrbList);
@@ -1434,7 +1434,7 @@ XhciDelAllAsyncIntTransfers (
//
Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
DEBUG ((DEBUG_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
}
RemoveEntryList (&Urb->UrbList);
@@ -1644,7 +1644,7 @@ XhcMonitorAsyncRequests (
//
Status = XhcFlushAsyncIntMap (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
DEBUG ((DEBUG_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
}
//
@@ -2139,11 +2139,11 @@ XhcInitializeDeviceSlot (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -2296,7 +2296,7 @@ XhcInitializeDeviceSlot (
);
if (!EFI_ERROR (Status)) {
DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));
@@ -2352,11 +2352,11 @@ XhcInitializeDeviceSlot64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -2509,7 +2509,7 @@ XhcInitializeDeviceSlot64 (
);
if (!EFI_ERROR (Status)) {
DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));
@@ -2556,7 +2556,7 @@ XhcDisableSlotCmd (
Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -2564,7 +2564,7 @@ XhcDisableSlotCmd (
//
// Construct the disable slot command
//
DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
@@ -2577,7 +2577,7 @@ XhcDisableSlotCmd (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
//
@@ -2663,7 +2663,7 @@ XhcDisableSlotCmd64 (
Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -2671,7 +2671,7 @@ XhcDisableSlotCmd64 (
//
// Construct the disable slot command
//
DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
@@ -2684,7 +2684,7 @@ XhcDisableSlotCmd64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
//
@@ -2851,7 +2851,7 @@ XhcInitializeEndpointContext (
//
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -2903,9 +2903,9 @@ XhcInitializeEndpointContext (
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -3043,7 +3043,7 @@ XhcInitializeEndpointContext64 (
//
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -3095,9 +3095,9 @@ XhcInitializeEndpointContext64 (
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -3192,7 +3192,7 @@ XhcSetConfigCmd (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3200,7 +3200,7 @@ XhcSetConfigCmd (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
} else {
Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
}
@@ -3282,7 +3282,7 @@ XhcSetConfigCmd64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3290,7 +3290,7 @@ XhcSetConfigCmd64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
} else {
Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
}
@@ -3323,7 +3323,7 @@ XhcStopEndpoint (
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
DEBUG ((EFI_D_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// When XhcCheckUrbResult waits for the Stop_Endpoint completion, it also checks
@@ -3363,7 +3363,7 @@ XhcStopEndpoint (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
Xhc->PendingUrb = NULL;
@@ -3394,7 +3394,7 @@ XhcResetEndpoint (
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
CMD_TRB_RESET_ENDPOINT CmdTrbResetED;
DEBUG ((EFI_D_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -3411,7 +3411,7 @@ XhcResetEndpoint (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
return Status;
@@ -3444,7 +3444,7 @@ XhcSetTrDequeuePointer (
CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
EFI_PHYSICAL_ADDRESS PhyAddr;
DEBUG ((EFI_D_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
DEBUG ((DEBUG_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -3464,7 +3464,7 @@ XhcSetTrDequeuePointer (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
return Status;
@@ -3652,7 +3652,7 @@ XhcSetInterface (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "SetInterface: Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "SetInterface: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3660,7 +3660,7 @@ XhcSetInterface (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
} else {
//
// Update the active AlternateSetting.
@@ -3854,7 +3854,7 @@ XhcSetInterface64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "SetInterface64: Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "SetInterface64: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3862,7 +3862,7 @@ XhcSetInterface64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
} else {
//
// Update the active AlternateSetting.
@@ -3916,7 +3916,7 @@ XhcEvaluateContext (
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Evaluate context\n"));
DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
@@ -3924,7 +3924,7 @@ XhcEvaluateContext (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
return Status;
}
@@ -3971,7 +3971,7 @@ XhcEvaluateContext64 (
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Evaluate context\n"));
DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
@@ -3979,7 +3979,7 @@ XhcEvaluateContext64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
return Status;
}
@@ -4040,7 +4040,7 @@ XhcConfigHubContext (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -4048,7 +4048,7 @@ XhcConfigHubContext (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
}
@@ -4108,7 +4108,7 @@ XhcConfigHubContext64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -4116,9 +4116,7 @@ XhcConfigHubContext64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
}

59
MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
View File

@@ -386,7 +386,7 @@ XhcPeiResetHC (
MicroSecondDelay (1000);
Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcPeiResetHC: %r\n", Status));
return Status;
}
@@ -410,7 +410,7 @@ XhcPeiHaltHC (
XhcPeiClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
DEBUG ((EFI_D_INFO, "XhcPeiHaltHC: %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcPeiHaltHC: %r\n", Status));
return Status;
}
@@ -434,7 +434,7 @@ XhcPeiRunHC (
XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
DEBUG ((EFI_D_INFO, "XhcPeiRunHC: %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcPeiRunHC: %r\n", Status));
return Status;
}
@@ -544,7 +544,7 @@ XhcPeiControlTransfer (
Len = 0;
if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: HC is halted or has system error\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiControlTransfer: HC is halted or has system error\n"));
goto ON_EXIT;
}
@@ -611,7 +611,7 @@ XhcPeiControlTransfer (
);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: failed to create URB"));
DEBUG ((DEBUG_ERROR, "XhcPeiControlTransfer: failed to create URB"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
@@ -631,7 +631,7 @@ XhcPeiControlTransfer (
//
RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);
if (EFI_ERROR(RecoveryStatus)) {
DEBUG((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
DEBUG((DEBUG_ERROR, "XhcPeiControlTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
}
XhcPeiFreeUrb (Xhc, Urb);
goto ON_EXIT;
@@ -641,7 +641,7 @@ XhcPeiControlTransfer (
} else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {
RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);
if (EFI_ERROR (RecoveryStatus)) {
DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiControlTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
}
Status = EFI_DEVICE_ERROR;
XhcPeiFreeUrb (Xhc, Urb);
@@ -718,7 +718,7 @@ XhcPeiControlTransfer (
// Don't support multi-TT feature for super speed hub now.
//
MTT = 0;
DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
DEBUG ((DEBUG_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
} else {
MTT = 0;
}
@@ -825,7 +825,7 @@ XhcPeiControlTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcPeiControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
return Status;
@@ -911,7 +911,7 @@ XhcPeiBulkTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: HC is halted or has system error\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiBulkTransfer: HC is halted or has system error\n"));
goto ON_EXIT;
}
@@ -942,7 +942,7 @@ XhcPeiBulkTransfer (
);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: failed to create URB\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiBulkTransfer: failed to create URB\n"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
@@ -958,7 +958,7 @@ XhcPeiBulkTransfer (
//
RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);
if (EFI_ERROR(RecoveryStatus)) {
DEBUG((EFI_D_ERROR, "XhcPeiBulkTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
DEBUG((DEBUG_ERROR, "XhcPeiBulkTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
}
} else {
if (*TransferResult == EFI_USB_NOERROR) {
@@ -966,7 +966,7 @@ XhcPeiBulkTransfer (
} else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {
RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);
if (EFI_ERROR (RecoveryStatus)) {
DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiBulkTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
}
Status = EFI_DEVICE_ERROR;
}
@@ -977,7 +977,7 @@ XhcPeiBulkTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcPeiBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
return Status;
@@ -1011,7 +1011,7 @@ XhcPeiGetRootHubPortNumber (
}
*PortNumber = XhcDev->HcSParams1.Data.MaxPorts;
DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortNumber: PortNumber = %x\n", *PortNumber));
DEBUG ((DEBUG_INFO, "XhcPeiGetRootHubPortNumber: PortNumber = %x\n", *PortNumber));
return EFI_SUCCESS;
}
@@ -1054,7 +1054,7 @@ XhcPeiClearRootHubPortFeature (
Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
State = XhcPeiReadOpReg (Xhc, Offset);
DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
DEBUG ((DEBUG_INFO, "XhcPeiClearRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
//
// Mask off the port status change bits, these bits are
@@ -1148,7 +1148,7 @@ XhcPeiClearRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));
DEBUG ((DEBUG_INFO, "XhcPeiClearRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));
return Status;
}
@@ -1189,7 +1189,7 @@ XhcPeiSetRootHubPortFeature (
Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
State = XhcPeiReadOpReg (Xhc, Offset);
DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
DEBUG ((DEBUG_INFO, "XhcPeiSetRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
//
// Mask off the port status change bits, these bits are
@@ -1256,7 +1256,7 @@ XhcPeiSetRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));
DEBUG ((DEBUG_INFO, "XhcPeiSetRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));
return Status;
}
@@ -1307,7 +1307,7 @@ XhcPeiGetRootHubPortStatus (
Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
State = XhcPeiReadOpReg (Xhc, Offset);
DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x State: %x\n", PortNumber, State));
DEBUG ((DEBUG_INFO, "XhcPeiGetRootHubPortStatus: Port: %x State: %x\n", PortNumber, State));
//
// According to XHCI 1.1 spec November 2017,
@@ -1371,7 +1371,7 @@ XhcPeiGetRootHubPortStatus (
ParentRouteChart.Dword = 0;
XhcPeiPollPortStatusChange (Xhc, ParentRouteChart, PortNumber, PortStatus);
DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: PortChangeStatus: %x PortStatus: %x\n", PortStatus->PortChangeStatus, PortStatus->PortStatus));
DEBUG ((DEBUG_INFO, "XhcPeiGetRootHubPortStatus: PortChangeStatus: %x PortStatus: %x\n", PortStatus->PortChangeStatus, PortStatus->PortStatus));
return EFI_SUCCESS;
}
@@ -1501,14 +1501,14 @@ XhcPeimEntry (
PageSize = XhcPeiReadOpReg (XhcDev, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
XhcDev->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
DEBUG ((EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress));
DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength));
DEBUG ((EFI_D_INFO, "XhciPei: HcSParams1: %x\n", XhcDev->HcSParams1.Dword));
DEBUG ((EFI_D_INFO, "XhciPei: HcSParams2: %x\n", XhcDev->HcSParams2.Dword));
DEBUG ((EFI_D_INFO, "XhciPei: HcCParams: %x\n", XhcDev->HcCParams.Dword));
DEBUG ((EFI_D_INFO, "XhciPei: DBOff: %x\n", XhcDev->DBOff));
DEBUG ((EFI_D_INFO, "XhciPei: RTSOff: %x\n", XhcDev->RTSOff));
DEBUG ((EFI_D_INFO, "XhciPei: PageSize: %x\n", XhcDev->PageSize));
DEBUG ((DEBUG_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress));
DEBUG ((DEBUG_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength));
DEBUG ((DEBUG_INFO, "XhciPei: HcSParams1: %x\n", XhcDev->HcSParams1.Dword));
DEBUG ((DEBUG_INFO, "XhciPei: HcSParams2: %x\n", XhcDev->HcSParams2.Dword));
DEBUG ((DEBUG_INFO, "XhciPei: HcCParams: %x\n", XhcDev->HcCParams.Dword));
DEBUG ((DEBUG_INFO, "XhciPei: DBOff: %x\n", XhcDev->DBOff));
DEBUG ((DEBUG_INFO, "XhciPei: RTSOff: %x\n", XhcDev->RTSOff));
DEBUG ((DEBUG_INFO, "XhciPei: PageSize: %x\n", XhcDev->PageSize));
XhcPeiResetHC (XhcDev, XHC_RESET_TIMEOUT);
ASSERT (XhcPeiIsHalt (XhcDev));
@@ -1551,4 +1551,3 @@ XhcPeimEntry (
return EFI_SUCCESS;
}

121
MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
View File

@@ -81,7 +81,7 @@ XhcPeiCmdTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcPeiCmdTransfer: HC is halted or has system error\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiCmdTransfer: HC is halted or has system error\n"));
goto ON_EXIT;
}
@@ -90,7 +90,7 @@ XhcPeiCmdTransfer (
//
Urb = XhcPeiCreateCmdTrb (Xhc, CmdTrb);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "XhcPeiCmdTransfer: failed to create URB\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiCmdTransfer: failed to create URB\n"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
@@ -168,7 +168,7 @@ XhcPeiCreateUrb (
Status = XhcPeiCreateTransferTrb (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiCreateUrb: XhcPeiCreateTransferTrb Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiCreateUrb: XhcPeiCreateTransferTrb Failed, Status = %r\n", Status));
FreePool (Urb);
Urb = NULL;
}
@@ -439,7 +439,7 @@ XhcPeiCreateTransferTrb (
break;
default:
DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));
ASSERT (FALSE);
break;
}
@@ -478,14 +478,14 @@ XhcPeiRecoverHaltedEndpoint (
}
Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
DEBUG ((EFI_D_INFO, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId, Dci));
//
// 1) Send Reset endpoint command to transit from halt to stop state
//
Status = XhcPeiResetEndpoint (Xhc, SlotId, Dci);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -494,7 +494,7 @@ XhcPeiRecoverHaltedEndpoint (
//
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -537,14 +537,14 @@ XhcPeiDequeueTrbFromEndpoint (
}
Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
DEBUG ((EFI_D_INFO, "XhcPeiDequeueTrbFromEndpoint: Stop Slot = %x, Dci = %x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcPeiDequeueTrbFromEndpoint: Stop Slot = %x, Dci = %x\n", SlotId, Dci));
//
// 1) Send Stop endpoint command to stop endpoint.
//
Status = XhcPeiStopEndpoint (Xhc, SlotId, Dci);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -553,7 +553,7 @@ XhcPeiDequeueTrbFromEndpoint (
//
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiDequeueTrbFromEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -683,31 +683,31 @@ XhcPeiCheckUrbResult (
case TRB_COMPLETION_STALL_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_STALL;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcPeiCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_BABBLE_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcPeiCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_DATA_BUFFER_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcPeiCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_USB_TRANSACTION_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcPeiCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_SHORT_PACKET:
case TRB_COMPLETION_SUCCESS:
if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
DEBUG ((EFI_D_VERBOSE, "XhcPeiCheckUrbResult: short packet happens!\n"));
DEBUG ((DEBUG_VERBOSE, "XhcPeiCheckUrbResult: short packet happens!\n"));
}
TRBType = (UINT8) (TRBPtr->Type);
@@ -720,7 +720,7 @@ XhcPeiCheckUrbResult (
break;
default:
DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcPeiCheckUrbResult: Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
goto EXIT;
@@ -859,7 +859,7 @@ XhcPeiPollPortStatusChange (
UINT8 SlotId;
USB_DEV_ROUTE RouteChart;
DEBUG ((EFI_D_INFO, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState->PortChangeStatus, PortState->PortStatus));
DEBUG ((DEBUG_INFO, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState->PortChangeStatus, PortState->PortStatus));
Status = EFI_SUCCESS;
@@ -1081,11 +1081,11 @@ XhcPeiInitializeDeviceSlot (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8) EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -1238,11 +1238,11 @@ XhcPeiInitializeDeviceSlot (
);
if (!EFI_ERROR (Status)) {
DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress));
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
}
DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot, Status = %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot, Status = %r\n", Status));
return Status;
}
@@ -1292,11 +1292,11 @@ XhcPeiInitializeDeviceSlot64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -1449,11 +1449,11 @@ XhcPeiInitializeDeviceSlot64 (
);
if (!EFI_ERROR (Status)) {
DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress));
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
}
DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot, Status = %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot, Status = %r\n", Status));
return Status;
}
@@ -1493,7 +1493,7 @@ XhcPeiDisableSlotCmd (
Status = XhcPeiDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd: failed to disable child, ignore error\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -1501,7 +1501,7 @@ XhcPeiDisableSlotCmd (
//
// Construct the disable slot command
//
DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd: Disable device slot %d!\n", SlotId));
DEBUG ((DEBUG_INFO, "XhcPeiDisableSlotCmd: Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
@@ -1514,7 +1514,7 @@ XhcPeiDisableSlotCmd (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
//
@@ -1557,7 +1557,7 @@ XhcPeiDisableSlotCmd (
Xhc->UsbDevContext[SlotId].Enabled = FALSE;
Xhc->UsbDevContext[SlotId].SlotId = 0;
DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd: Disable Slot Command, Status = %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcPeiDisableSlotCmd: Disable Slot Command, Status = %r\n", Status));
return Status;
}
@@ -1596,7 +1596,7 @@ XhcPeiDisableSlotCmd64 (
Status = XhcPeiDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd64: failed to disable child, ignore error\n"));
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd64: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -1604,7 +1604,7 @@ XhcPeiDisableSlotCmd64 (
//
// Construct the disable slot command
//
DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd64: Disable device slot %d!\n", SlotId));
DEBUG ((DEBUG_INFO, "XhcPeiDisableSlotCmd64: Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
@@ -1617,7 +1617,7 @@ XhcPeiDisableSlotCmd64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
//
@@ -1660,7 +1660,7 @@ XhcPeiDisableSlotCmd64 (
Xhc->UsbDevContext[SlotId].Enabled = FALSE;
Xhc->UsbDevContext[SlotId].SlotId = 0;
DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd64: Disable Slot Command, Status = %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcPeiDisableSlotCmd64: Disable Slot Command, Status = %r\n", Status));
return Status;
}
@@ -1790,7 +1790,7 @@ XhcPeiSetConfigCmd (
//
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcPeiSetConfigCmd: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -1833,9 +1833,9 @@ XhcPeiSetConfigCmd (
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport Control EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcPeiSetConfigCmd: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unknown EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcPeiSetConfigCmd: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -1867,7 +1867,7 @@ XhcPeiSetConfigCmd (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "XhcSetConfigCmd: Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "XhcSetConfigCmd: Configure Endpoint\n"));
Status = XhcPeiCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -1875,7 +1875,7 @@ XhcPeiSetConfigCmd (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
}
@@ -2007,7 +2007,7 @@ XhcPeiSetConfigCmd64 (
//
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcPeiSetConfigCmd64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -2050,9 +2050,9 @@ XhcPeiSetConfigCmd64 (
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcPeiSetConfigCmd64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unknown EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcPeiSetConfigCmd64: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -2086,7 +2086,7 @@ XhcPeiSetConfigCmd64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "XhcSetConfigCmd64: Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "XhcSetConfigCmd64: Configure Endpoint\n"));
Status = XhcPeiCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -2094,7 +2094,7 @@ XhcPeiSetConfigCmd64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
@@ -2142,7 +2142,7 @@ XhcPeiEvaluateContext (
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "XhcEvaluateContext: Evaluate context\n"));
DEBUG ((DEBUG_INFO, "XhcEvaluateContext: Evaluate context\n"));
Status = XhcPeiCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
@@ -2150,7 +2150,7 @@ XhcPeiEvaluateContext (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
return Status;
}
@@ -2196,7 +2196,7 @@ XhcPeiEvaluateContext64 (
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "XhcEvaluateContext64: Evaluate context 64\n"));
DEBUG ((DEBUG_INFO, "XhcEvaluateContext64: Evaluate context 64\n"));
Status = XhcPeiCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
@@ -2204,7 +2204,7 @@ XhcPeiEvaluateContext64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
return Status;
}
@@ -2264,7 +2264,7 @@ XhcPeiConfigHubContext (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcPeiCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -2272,7 +2272,7 @@ XhcPeiConfigHubContext (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
}
@@ -2332,7 +2332,7 @@ XhcPeiConfigHubContext64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Hub Slot Context 64\n"));
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context 64\n"));
Status = XhcPeiCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -2340,7 +2340,7 @@ XhcPeiConfigHubContext64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
}
@@ -2368,7 +2368,7 @@ XhcPeiStopEndpoint (
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
DEBUG ((EFI_D_INFO, "XhcPeiStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcPeiStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -2385,7 +2385,7 @@ XhcPeiStopEndpoint (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
return Status;
@@ -2414,7 +2414,7 @@ XhcPeiResetEndpoint (
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
CMD_TRB_RESET_ENDPOINT CmdTrbResetED;
DEBUG ((EFI_D_INFO, "XhcPeiResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcPeiResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -2431,7 +2431,7 @@ XhcPeiResetEndpoint (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
return Status;
@@ -2464,7 +2464,7 @@ XhcPeiSetTrDequeuePointer (
CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
EFI_PHYSICAL_ADDRESS PhyAddr;
DEBUG ((EFI_D_INFO, "XhcPeiSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
DEBUG ((DEBUG_INFO, "XhcPeiSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -2484,7 +2484,7 @@ XhcPeiSetTrDequeuePointer (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcPeiSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcPeiSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
return Status;
@@ -2938,7 +2938,7 @@ XhcPeiInitSched (
XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));
XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
DEBUG ((EFI_D_INFO, "XhcPeiInitSched:DCBAA=0x%x\n", Xhc->DCBAA));
DEBUG ((DEBUG_INFO, "XhcPeiInitSched:DCBAA=0x%x\n", Xhc->DCBAA));
//
// Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
@@ -2962,7 +2962,7 @@ XhcPeiInitSched (
XhcPeiWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT (CmdRingPhy));
XhcPeiWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
DEBUG ((EFI_D_INFO, "XhcPeiInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
DEBUG ((DEBUG_INFO, "XhcPeiInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
//
// Disable the 'interrupter enable' bit in USB_CMD
@@ -2978,7 +2978,7 @@ XhcPeiInitSched (
// Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
//
XhcPeiCreateEventRing (Xhc, &Xhc->EventRing);
DEBUG ((EFI_D_INFO, "XhcPeiInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));
DEBUG ((DEBUG_INFO, "XhcPeiInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));
}
/**
@@ -3031,4 +3031,3 @@ XhcPeiFreeSched (
Xhc->MemPool = NULL;
}
}