sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

MdeModulePkg: Change use of EFI_D_* to DEBUG_*

Browse Source 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3739

Update all use of EFI_D_* defines in DEBUG() macros to DEBUG_* defines.

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael D Kinney
2021-11-16 19:21:29 -08:00
committed by mergify[bot]
parent 917e98f3e5
commit 87000d7708
146 changed files with 1560 additions and 1619 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
View File

@@ -128,13 +128,13 @@ WriteNvmeControllerConfiguration (
return Status;
}
DEBUG ((EFI_D_INFO, "Cc.En: %d\n", Cc->En));
DEBUG ((EFI_D_INFO, "Cc.Css: %d\n", Cc->Css));
DEBUG ((EFI_D_INFO, "Cc.Mps: %d\n", Cc->Mps));
DEBUG ((EFI_D_INFO, "Cc.Ams: %d\n", Cc->Ams));
DEBUG ((EFI_D_INFO, "Cc.Shn: %d\n", Cc->Shn));
DEBUG ((EFI_D_INFO, "Cc.Iosqes: %d\n", Cc->Iosqes));
DEBUG ((EFI_D_INFO, "Cc.Iocqes: %d\n", Cc->Iocqes));
DEBUG ((DEBUG_INFO, "Cc.En: %d\n", Cc->En));
DEBUG ((DEBUG_INFO, "Cc.Css: %d\n", Cc->Css));
DEBUG ((DEBUG_INFO, "Cc.Mps: %d\n", Cc->Mps));
DEBUG ((DEBUG_INFO, "Cc.Ams: %d\n", Cc->Ams));
DEBUG ((DEBUG_INFO, "Cc.Shn: %d\n", Cc->Shn));
DEBUG ((DEBUG_INFO, "Cc.Iosqes: %d\n", Cc->Iosqes));
DEBUG ((DEBUG_INFO, "Cc.Iocqes: %d\n", Cc->Iocqes));
return EFI_SUCCESS;
}
@@ -214,8 +214,8 @@ WriteNvmeAdminQueueAttributes (
return Status;
}
DEBUG ((EFI_D_INFO, "Aqa.Asqs: %d\n", Aqa->Asqs));
DEBUG ((EFI_D_INFO, "Aqa.Acqs: %d\n", Aqa->Acqs));
DEBUG ((DEBUG_INFO, "Aqa.Asqs: %d\n", Aqa->Asqs));
DEBUG ((DEBUG_INFO, "Aqa.Acqs: %d\n", Aqa->Acqs));
return EFI_SUCCESS;
}
@@ -257,7 +257,7 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
return Status;
}
DEBUG ((EFI_D_INFO, "Asq: %lx\n", *Asq));
DEBUG ((DEBUG_INFO, "Asq: %lx\n", *Asq));
return EFI_SUCCESS;
}
@@ -300,7 +300,7 @@ WriteNvmeAdminCompletionQueueBaseAddress (
return Status;
}
DEBUG ((EFI_D_INFO, "Acq: %lxh\n", *Acq));
DEBUG ((DEBUG_INFO, "Acq: %lxh\n", *Acq));
return EFI_SUCCESS;
}
@@ -379,7 +379,7 @@ NvmeDisableController (
);
}
DEBUG ((EFI_D_INFO, "NVMe controller is disabled with status [%r].\n", Status));
DEBUG ((DEBUG_INFO, "NVMe controller is disabled with status [%r].\n", Status));
return Status;
}
@@ -453,7 +453,7 @@ NvmeEnableController (
);
}
DEBUG ((EFI_D_INFO, "NVMe controller is enabled with status [%r].\n", Status));
DEBUG ((DEBUG_INFO, "NVMe controller is enabled with status [%r].\n", Status));
return Status;
}
@@ -764,7 +764,7 @@ NvmeControllerInit (
}
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_INFO, "NvmeControllerInit: failed to enable controller\n"));
DEBUG ((DEBUG_INFO, "NvmeControllerInit: failed to enable controller\n"));
return Status;
}
@@ -778,7 +778,7 @@ NvmeControllerInit (
NULL
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));
DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));
}
//
@@ -790,7 +790,7 @@ NvmeControllerInit (
}
if (Private->Cap.Css != 0x01) {
DEBUG ((EFI_D_INFO, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));
DEBUG ((DEBUG_INFO, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));
return EFI_UNSUPPORTED;
}
@@ -854,15 +854,15 @@ NvmeControllerInit (
Private->CqBuffer[2] = (NVME_CQ *)(UINTN)(Private->Buffer + 5 * EFI_PAGE_SIZE);
Private->CqBufferPciAddr[2] = (NVME_CQ *)(UINTN)(Private->BufferPciAddr + 5 * EFI_PAGE_SIZE);
DEBUG ((EFI_D_INFO, "Private->Buffer = [%016X]\n", (UINT64)(UINTN)Private->Buffer));
DEBUG ((EFI_D_INFO, "Admin Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));
DEBUG ((EFI_D_INFO, "Admin Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));
DEBUG ((EFI_D_INFO, "Admin Submission Queue (SqBuffer[0]) = [%016X]\n", Private->SqBuffer[0]));
DEBUG ((EFI_D_INFO, "Admin Completion Queue (CqBuffer[0]) = [%016X]\n", Private->CqBuffer[0]));
DEBUG ((EFI_D_INFO, "Sync I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private->SqBuffer[1]));
DEBUG ((EFI_D_INFO, "Sync I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private->CqBuffer[1]));
DEBUG ((EFI_D_INFO, "Async I/O Submission Queue (SqBuffer[2]) = [%016X]\n", Private->SqBuffer[2]));
DEBUG ((EFI_D_INFO, "Async I/O Completion Queue (CqBuffer[2]) = [%016X]\n", Private->CqBuffer[2]));
DEBUG ((DEBUG_INFO, "Private->Buffer = [%016X]\n", (UINT64)(UINTN)Private->Buffer));
DEBUG ((DEBUG_INFO, "Admin Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));
DEBUG ((DEBUG_INFO, "Admin Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));
DEBUG ((DEBUG_INFO, "Admin Submission Queue (SqBuffer[0]) = [%016X]\n", Private->SqBuffer[0]));
DEBUG ((DEBUG_INFO, "Admin Completion Queue (CqBuffer[0]) = [%016X]\n", Private->CqBuffer[0]));
DEBUG ((DEBUG_INFO, "Sync I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private->SqBuffer[1]));
DEBUG ((DEBUG_INFO, "Sync I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private->CqBuffer[1]));
DEBUG ((DEBUG_INFO, "Async I/O Submission Queue (SqBuffer[2]) = [%016X]\n", Private->SqBuffer[2]));
DEBUG ((DEBUG_INFO, "Async I/O Completion Queue (CqBuffer[2]) = [%016X]\n", Private->CqBuffer[2]));
//
// Program admin queue attributes.
@@ -925,20 +925,20 @@ NvmeControllerInit (
Sn[20] = 0;
CopyMem (Mn, Private->ControllerData->Mn, sizeof (Private->ControllerData->Mn));
Mn[40] = 0;
DEBUG ((EFI_D_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((EFI_D_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
DEBUG ((EFI_D_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
DEBUG ((EFI_D_INFO, " SN : %a\n", Sn));
DEBUG ((EFI_D_INFO, " MN : %a\n", Mn));
DEBUG ((EFI_D_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64*)(Private->ControllerData->Tnvmcap + 8))));
DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64*)Private->ControllerData->Tnvmcap)));
DEBUG ((EFI_D_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
DEBUG ((EFI_D_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
DEBUG ((EFI_D_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
DEBUG ((EFI_D_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
DEBUG ((EFI_D_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
DEBUG ((EFI_D_INFO, " NN : 0x%x\n", Private->ControllerData->Nn));
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
DEBUG ((DEBUG_INFO, " NN : 0x%x\n", Private->ControllerData->Nn));
//
// Create two I/O completion queues.