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MdeModulePkg: Change use of EFI_D_* to DEBUG_*

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3739

Update all use of EFI_D_* defines in DEBUG() macros to DEBUG_* defines.

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael D Kinney
2021-11-16 19:21:29 -08:00
committed by mergify[bot]
parent 917e98f3e5
commit 87000d7708
146 changed files with 1560 additions and 1619 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
View File

@@ -503,7 +503,7 @@ UsbHcAllocateMem (
NewBlock = UsbHcAllocMemBlock (Pool, Pages);
if (NewBlock == NULL) {
DEBUG ((EFI_D_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
DEBUG ((DEBUG_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
return NULL;
}

63
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
View File

@@ -120,7 +120,7 @@ XhcGetCapability (
*MaxSpeed = EFI_USB_SPEED_SUPER;
*PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts);
*Is64BitCapable = (UINT8) Xhc->Support64BitDma;
DEBUG ((EFI_D_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
DEBUG ((DEBUG_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
gBS->RestoreTPL (OldTpl);
@@ -216,7 +216,7 @@ XhcReset (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcReset: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcReset: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -260,7 +260,7 @@ XhcGetState (
*State = EfiUsbHcStateOperational;
}
DEBUG ((EFI_D_INFO, "XhcGetState: current state %d\n", *State));
DEBUG ((DEBUG_INFO, "XhcGetState: current state %d\n", *State));
gBS->RestoreTPL (OldTpl);
return EFI_SUCCESS;
@@ -336,7 +336,7 @@ XhcSetState (
Status = EFI_INVALID_PARAMETER;
}
DEBUG ((EFI_D_INFO, "XhcSetState: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcSetState: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -530,7 +530,7 @@ XhcSetRootHubPortFeature (
break;
case EfiUsbPortReset:
DEBUG ((EFI_D_INFO, "XhcUsbPortReset!\n"));
DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));
//
// Make sure Host Controller not halt before reset it
//
@@ -538,7 +538,7 @@ XhcSetRootHubPortFeature (
Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
break;
}
}
@@ -571,7 +571,7 @@ XhcSetRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -706,7 +706,7 @@ XhcClearRootHubPortFeature (
}
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));
DEBUG ((DEBUG_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -914,7 +914,7 @@ XhcControlTransfer (
Len = 0;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcControlTransfer: HC halted at entrance\n"));
DEBUG ((DEBUG_ERROR, "XhcControlTransfer: HC halted at entrance\n"));
goto ON_EXIT;
}
@@ -1043,7 +1043,7 @@ XhcControlTransfer (
// Don't support multi-TT feature for super speed hub now.
//
MTT = 0;
DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
DEBUG ((DEBUG_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
} else {
MTT = 0;
}
@@ -1162,7 +1162,7 @@ XhcControlTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
gBS->RestoreTPL (OldTpl);
@@ -1250,7 +1250,7 @@ XhcBulkTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: HC is halted\n"));
DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: HC is halted\n"));
goto ON_EXIT;
}
@@ -1282,7 +1282,7 @@ XhcBulkTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
gBS->RestoreTPL (OldTpl);
@@ -1386,14 +1386,14 @@ XhcAsyncInterruptTransfer (
}
Status = XhciDelAsyncIntTransfer (Xhc, DeviceAddress, EndPointAddress);
DEBUG ((EFI_D_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));
DEBUG ((DEBUG_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));
goto ON_EXIT;
}
Status = EFI_SUCCESS;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));
DEBUG ((DEBUG_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));
Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
@@ -1508,7 +1508,7 @@ XhcSyncInterruptTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
DEBUG ((DEBUG_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
goto ON_EXIT;
}
@@ -1536,7 +1536,7 @@ XhcSyncInterruptTransfer (
ON_EXIT:
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
DEBUG ((DEBUG_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
gBS->RestoreTPL (OldTpl);
@@ -1805,14 +1805,14 @@ XhcCreateUsbHc (
Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
//
// Create AsyncRequest Polling Timer
@@ -1972,7 +1972,7 @@ XhcDriverBindingStart (
}
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));
goto CLOSE_PCIIO;
}
@@ -1982,7 +1982,7 @@ XhcDriverBindingStart (
Xhc = XhcCreateUsbHc (PciIo, HcDevicePath, OriginalPciAttributes);
if (Xhc == NULL) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));
return EFI_OUT_OF_RESOURCES;
}
@@ -2000,7 +2000,7 @@ XhcDriverBindingStart (
if (!EFI_ERROR (Status)) {
Xhc->Support64BitDma = TRUE;
} else {
DEBUG ((EFI_D_WARN,
DEBUG ((DEBUG_WARN,
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
__FUNCTION__, Controller, Status));
}
@@ -2032,7 +2032,7 @@ XhcDriverBindingStart (
//
Status = gBS->SetTimer (Xhc->PollTimer, TimerPeriodic, XHC_ASYNC_TIMER_INTERVAL);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));
XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
goto FREE_POOL;
}
@@ -2078,11 +2078,11 @@ XhcDriverBindingStart (
&Xhc->Usb2Hc
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
goto FREE_POOL;
}
DEBUG ((EFI_D_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));
DEBUG ((DEBUG_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));
return EFI_SUCCESS;
FREE_POOL:
@@ -2233,4 +2233,3 @@ XhcDriverBindingStop (
return EFI_SUCCESS;
}

25
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
View File

@@ -38,7 +38,7 @@ XhcReadCapReg8 (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFF;
}
@@ -74,7 +74,7 @@ XhcReadCapReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -112,7 +112,7 @@ XhcReadOpReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -148,7 +148,7 @@ XhcWriteOpReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -185,7 +185,7 @@ XhcWriteDoorBellReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -219,7 +219,7 @@ XhcReadRuntimeReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -255,7 +255,7 @@ XhcWriteRuntimeReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -289,7 +289,7 @@ XhcReadExtCapReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -325,7 +325,7 @@ XhcWriteExtCapReg (
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
DEBUG ((DEBUG_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -508,7 +508,7 @@ XhcSetBiosOwnership (
return;
}
DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
DEBUG ((DEBUG_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);
@@ -532,7 +532,7 @@ XhcClearBiosOwnership (
return;
}
DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
DEBUG ((DEBUG_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);
@@ -666,7 +666,7 @@ XhcResetHC (
Status = EFI_SUCCESS;
DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
DEBUG ((DEBUG_INFO, "XhcResetHC!\n"));
//
// Host can only be reset when it is halt. If not so, halt it
//
@@ -748,4 +748,3 @@ XhcRunHC (
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
return Status;
}

122
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

@@ -82,7 +82,7 @@ XhcCmdTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: HC is halted\n"));
goto ON_EXIT;
}
@@ -92,7 +92,7 @@ XhcCmdTransfer (
Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
if (Urb == NULL) {
DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: failed to create URB\n"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
@@ -172,7 +172,7 @@ XhcCreateUrb (
Status = XhcCreateTransferTrb (Xhc, Urb);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
FreePool (Urb);
Urb = NULL;
}
@@ -269,7 +269,7 @@ XhcCreateTransferTrb (
Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
return EFI_OUT_OF_RESOURCES;
}
@@ -446,7 +446,7 @@ XhcCreateTransferTrb (
break;
default:
DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));
ASSERT (FALSE);
break;
}
@@ -582,7 +582,7 @@ XhcInitSched (
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
DEBUG ((DEBUG_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
//
// Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
@@ -660,14 +660,14 @@ XhcRecoverHaltedEndpoint (
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
//
// 1) Send Reset endpoint command to transit from halt to stop state
//
Status = XhcResetEndpoint(Xhc, SlotId, Dci);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -676,7 +676,7 @@ XhcRecoverHaltedEndpoint (
//
Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -722,14 +722,14 @@ XhcDequeueTrbFromEndpoint (
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
//
// 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
//
Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -1159,25 +1159,25 @@ XhcCheckUrbResult (
case TRB_COMPLETION_STALL_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_STALL;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_BABBLE_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_DATA_BUFFER_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_USB_TRANSACTION_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_STOPPED:
@@ -1193,7 +1193,7 @@ XhcCheckUrbResult (
case TRB_COMPLETION_SHORT_PACKET:
case TRB_COMPLETION_SUCCESS:
if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
DEBUG ((DEBUG_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
}
TRBType = (UINT8) (TRBPtr->Type);
@@ -1206,7 +1206,7 @@ XhcCheckUrbResult (
break;
default:
DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
goto EXIT;
@@ -1396,7 +1396,7 @@ XhciDelAsyncIntTransfer (
//
Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
DEBUG ((DEBUG_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
}
RemoveEntryList (&Urb->UrbList);
@@ -1434,7 +1434,7 @@ XhciDelAllAsyncIntTransfers (
//
Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
DEBUG ((DEBUG_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
}
RemoveEntryList (&Urb->UrbList);
@@ -1644,7 +1644,7 @@ XhcMonitorAsyncRequests (
//
Status = XhcFlushAsyncIntMap (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
DEBUG ((DEBUG_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
}
//
@@ -2139,11 +2139,11 @@ XhcInitializeDeviceSlot (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -2296,7 +2296,7 @@ XhcInitializeDeviceSlot (
);
if (!EFI_ERROR (Status)) {
DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));
@@ -2352,11 +2352,11 @@ XhcInitializeDeviceSlot64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -2509,7 +2509,7 @@ XhcInitializeDeviceSlot64 (
);
if (!EFI_ERROR (Status)) {
DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));
@@ -2556,7 +2556,7 @@ XhcDisableSlotCmd (
Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -2564,7 +2564,7 @@ XhcDisableSlotCmd (
//
// Construct the disable slot command
//
DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
@@ -2577,7 +2577,7 @@ XhcDisableSlotCmd (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
//
@@ -2663,7 +2663,7 @@ XhcDisableSlotCmd64 (
Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -2671,7 +2671,7 @@ XhcDisableSlotCmd64 (
//
// Construct the disable slot command
//
DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
@@ -2684,7 +2684,7 @@ XhcDisableSlotCmd64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
//
@@ -2851,7 +2851,7 @@ XhcInitializeEndpointContext (
//
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -2903,9 +2903,9 @@ XhcInitializeEndpointContext (
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -3043,7 +3043,7 @@ XhcInitializeEndpointContext64 (
//
// Do not support isochronous transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -3095,9 +3095,9 @@ XhcInitializeEndpointContext64 (
//
// Do not support control transfer now.
//
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -3192,7 +3192,7 @@ XhcSetConfigCmd (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3200,7 +3200,7 @@ XhcSetConfigCmd (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
} else {
Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
}
@@ -3282,7 +3282,7 @@ XhcSetConfigCmd64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3290,7 +3290,7 @@ XhcSetConfigCmd64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
} else {
Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
}
@@ -3323,7 +3323,7 @@ XhcStopEndpoint (
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
DEBUG ((EFI_D_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// When XhcCheckUrbResult waits for the Stop_Endpoint completion, it also checks
@@ -3363,7 +3363,7 @@ XhcStopEndpoint (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
Xhc->PendingUrb = NULL;
@@ -3394,7 +3394,7 @@ XhcResetEndpoint (
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
CMD_TRB_RESET_ENDPOINT CmdTrbResetED;
DEBUG ((EFI_D_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
DEBUG ((DEBUG_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -3411,7 +3411,7 @@ XhcResetEndpoint (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
return Status;
@@ -3444,7 +3444,7 @@ XhcSetTrDequeuePointer (
CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
EFI_PHYSICAL_ADDRESS PhyAddr;
DEBUG ((EFI_D_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
DEBUG ((DEBUG_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -3464,7 +3464,7 @@ XhcSetTrDequeuePointer (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
return Status;
@@ -3652,7 +3652,7 @@ XhcSetInterface (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "SetInterface: Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "SetInterface: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3660,7 +3660,7 @@ XhcSetInterface (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
} else {
//
// Update the active AlternateSetting.
@@ -3854,7 +3854,7 @@ XhcSetInterface64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "SetInterface64: Configure Endpoint\n"));
DEBUG ((DEBUG_INFO, "SetInterface64: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -3862,7 +3862,7 @@ XhcSetInterface64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
} else {
//
// Update the active AlternateSetting.
@@ -3916,7 +3916,7 @@ XhcEvaluateContext (
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Evaluate context\n"));
DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
@@ -3924,7 +3924,7 @@ XhcEvaluateContext (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
return Status;
}
@@ -3971,7 +3971,7 @@ XhcEvaluateContext64 (
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Evaluate context\n"));
DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
@@ -3979,7 +3979,7 @@ XhcEvaluateContext64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
return Status;
}
@@ -4040,7 +4040,7 @@ XhcConfigHubContext (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -4048,7 +4048,7 @@ XhcConfigHubContext (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
}
@@ -4108,7 +4108,7 @@ XhcConfigHubContext64 (
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
Xhc,
(TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
@@ -4116,9 +4116,7 @@ XhcConfigHubContext64 (
(TRB_TEMPLATE **) (UINTN) &EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
return Status;
}