Initial import.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3 6f19259b-4bc3-4df7-8a09-765794883524
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bbahnsen
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EdkModulePkg/Core/DxeIplPeim/x64/VirtualMemory.h
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EdkModulePkg/Core/DxeIplPeim/x64/VirtualMemory.h
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/*++
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Copyright (c) 2006, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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VirtualMemory.h
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Abstract:
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x64 Long Mode Virtual Memory Management Definitions
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References:
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1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
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--*/
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#ifndef _VIRTUAL_MEMORY_H_
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#define _VIRTUAL_MEMORY_H_
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#pragma pack(1)
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Reserved:1; // Reserved
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UINT64 MustBeZero:2; // Must Be Zero
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;
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//
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// Page-Directory Offset 4K
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Reserved:1; // Reserved
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UINT64 MustBeZero:1; // Must Be Zero
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UINT64 Reserved2:1; // Reserved
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} x64_PAGE_DIRECTORY_ENTRY_4K;
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//
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// Page Table Entry 4K
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 PAT:1; // 0 = Ignore Page Attribute Table
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} x64_PAGE_TABLE_ENTRY_4K;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:8; // Must be zero;
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UINT64 PageTableBaseAddress:31; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} x64_PAGE_TABLE_ENTRY_2M;
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typedef union {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 Reserved:57;
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} x64_PAGE_TABLE_ENTRY_COMMON;
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typedef union {
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x64_PAGE_TABLE_ENTRY_4K Page4k;
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x64_PAGE_TABLE_ENTRY_2M Page2Mb;
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x64_PAGE_TABLE_ENTRY_COMMON Common;
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} x64_PAGE_TABLE_ENTRY;
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//
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// MTRR Definitions
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//
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typedef enum {
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Uncached = 0,
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WriteCombining = 1,
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WriteThrough = 4,
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WriteProtected = 5,
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WriteBack = 6
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} x64_MTRR_MEMORY_TYPE;
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typedef union {
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struct {
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UINT32 VCNT:8; // The number of Variable Range MTRRs
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UINT32 FIX:1; // 1=Fixed Range MTRRs supported. 0=Fixed Range MTRRs not supported
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UINT32 Reserved_0; // Reserved
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UINT32 WC:1; // Write combining memory type supported
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UINT32 Reserved_1:21; // Reserved
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UINT32 Reserved_2:32; // Reserved
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} Bits;
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UINT64 Uint64;
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} x64_MTRRCAP_MSR;
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typedef union {
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struct {
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UINT32 Type:8; // Default Memory Type
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UINT32 Reserved_0:2; // Reserved
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UINT32 FE:1; // 1=Fixed Range MTRRs enabled. 0=Fixed Range MTRRs disabled
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UINT32 E:1; // 1=MTRRs enabled, 0=MTRRs disabled
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UINT32 Reserved_1:20; // Reserved
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UINT32 Reserved_2:32; // Reserved
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} Bits;
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UINT64 Uint64;
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} x64_MTRR_DEF_TYPE_MSR;
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typedef union {
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UINT8 Type[8]; // The 8 Memory Type values in the 64-bit MTRR
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UINT64 Uint64; // The full 64-bit MSR
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} x64_MTRR_FIXED_RANGE_MSR;
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typedef struct {
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x64_MTRRCAP_MSR Capabilities; // MTRR Capabilities MSR value
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x64_MTRR_DEF_TYPE_MSR DefaultType; // Default Memory Type MSR Value
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x64_MTRR_FIXED_RANGE_MSR Fixed[11]; // The 11 Fixed MTRR MSR Values
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} x64_MTRR_FIXED_RANGE;
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typedef union {
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struct {
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UINT64 Type:8; // Memory Type
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UINT64 Reserved0:4; // Reserved
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UINT64 PhysBase:40; // The physical base address(bits 35..12) of the MTRR
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UINT64 Reserved1:12 ; // Reserved
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} Bits;
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UINT64 Uint64;
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} x64_MTRR_PHYSBASE_MSR;
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typedef union {
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struct {
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UINT64 Reserved0:11; // Reserved
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UINT64 Valid:1; // 1=MTRR is valid, 0=MTRR is not valid
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UINT64 PhysMask:40; // The physical address mask (bits 35..12) of the MTRR
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UINT64 Reserved1:12; // Reserved
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} Bits;
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UINT64 Uint64;
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} x64_MTRR_PHYSMASK_MSR;
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typedef struct {
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x64_MTRR_PHYSBASE_MSR PhysBase; // Variable MTRR Physical Base MSR
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x64_MTRR_PHYSMASK_MSR PhysMask; // Variable MTRR Physical Mask MSR
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} x64_MTRR_VARIABLE_RANGE;
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#pragma pack()
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x64_MTRR_MEMORY_TYPE
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EfiGetMTRRMemoryType (
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IN EFI_PHYSICAL_ADDRESS Address
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)
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;
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BOOLEAN
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CanNotUse2MBPage (
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IN EFI_PHYSICAL_ADDRESS BaseAddress
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)
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;
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VOID
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Convert2MBPageTo4KPages (
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IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB,
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IN EFI_PHYSICAL_ADDRESS PageAddress
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)
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;
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EFI_PHYSICAL_ADDRESS
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CreateIdentityMappingPageTables (
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IN UINT32 NumberOfProcessorPhysicalAddressBits
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)
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;
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#endif
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