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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3 6f19259b-4bc3-4df7-8a09-765794883524
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bbahnsen
2006-04-21 22:54:32 +00:00
commit 878ddf1fc3
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101
MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c Normal file
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/** @file
Base Library CPU functions for Itanium
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
//void __mfa (void);
#pragma intrinsic (_enable)
#pragma intrinsic (_disable)
#pragma intrinsic (__break)
#pragma intrinsic (__mfa)
/**
Generates a breakpoint on the CPU.
Generates a breakpoint on the CPU. The breakpoint must be implemented such
that code can resume normal execution after the breakpoint.
**/
VOID
EFIAPI
CpuBreakpoint (
VOID
)
{
__break (0);
}
/**
Used to serialize load and store operations.
All loads and stores that proceed calls to this function are guaranteed to be
globally visible when this function returns.
**/
VOID
EFIAPI
MemoryFence (
VOID
)
{
__mfa ();
}
/**
Disables CPU interrupts.
Disables CPU interrupts.
**/
VOID
EFIAPI
DisableInterrupts (
VOID
)
{
_disable ();
}
/**
Enables CPU interrupts.
Enables CPU interrupts.
**/
VOID
EFIAPI
EnableInterrupts (
VOID
)
{
_enable ();
}
/**
Retrieves the current CPU interrupt state.
Retrieves the current CPU interrupt state. Returns TRUE is interrupts are
currently enabled. Otherwise returns FALSE.
@retval TRUE CPU interrupts are enabled.
@retval FALSE CPU interrupts are disabled.
**/
BOOLEAN
EFIAPI
GetInterruptState (
VOID
)
{
return FALSE;
}

29
MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange32.s Normal file
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/// @file
/// Contains an implementation of InterlockedCompareExchange32 on Itanium-
/// based architecture.
///
/// Copyright (c) 2006, Intel Corporation
/// All rights reserved. This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: InterlockedCompareExchange32.s
///
///
.auto
.text
.proc InternalSyncCompareExchange32
.type InternalSyncCompareExchange32, @function
InternalSyncCompareExchange32::
zxt4 r33 = r33
mov ar.ccv = r33
cmpxchg4.rel r8 = [r32], r34
mf
br.ret.sptk.many b0
.endp InternalSyncCompareExchange32

28
MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange64.s Normal file
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/// @file
/// Contains an implementation of InterlockedCompareExchange64 on Itanium-
/// based architecture.
///
/// Copyright (c) 2006, Intel Corporation
/// All rights reserved. This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: InterlockedCompareExchange64.s
///
///
.auto
.text
.proc InternalSyncCompareExchange64
.type InternalSyncCompareExchange64, @function
InternalSyncCompareExchange64::
mov ar.ccv = r33
cmpxchg8.rel r8 = [r64], r34
mf
br.ret.sptk.many b0
.endp InternalSyncCompareExchange64

122
MdePkg/Library/BaseLib/Ipf/SwitchStack.s Normal file
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//++
// Copyright (c) 2006, Intel Corporation
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Module Name:
//
// SwitchStack.s
//
// Abstract:
//
// Contains an implementation of a stack switch for the Itanium-based architecture.
//
//
//
// Revision History:
//
//--
.file "SwitchStack.s"
#include "asm.h"
#include "ia_64gen.h"
// Define hardware RSE Configuration Register
//
// RS Configuration (RSC) bit field positions
#define RSC_MODE 0
#define RSC_PL 2
#define RSC_BE 4
// RSC bits 5-15 reserved
#define RSC_MBZ0 5
#define RSC_MBZ0_V 0x3ff
#define RSC_LOADRS 16
#define RSC_LOADRS_LEN 14
// RSC bits 30-63 reserved
#define RSC_MBZ1 30
#define RSC_MBZ1_V 0x3ffffffffULL
// RSC modes
// Lazy
#define RSC_MODE_LY (0x0)
// Store intensive
#define RSC_MODE_SI (0x1)
// Load intensive
#define RSC_MODE_LI (0x2)
// Eager
#define RSC_MODE_EA (0x3)
// RSC Endian bit values
#define RSC_BE_LITTLE 0
#define RSC_BE_BIG 1
// RSC while in kernel: enabled, little endian, pl = 0, eager mode
#define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
#define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
// RSE disabled: disabled, pl = 0, little endian, eager mode
#define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
//VOID
//SwitchStack (
// VOID *ContinuationFunction,
// UINTN Parameter,
// UINTN NewTopOfStack,
// UINTN NewBSPStore OPTIONAL
//)
///*++
//
//Input Arguments
//
// ContinuationFunction - This is a pointer to the PLABEL of the function that should be called once the
// new stack has been created.
// Parameter - The parameter to pass to the continuation function
// NewTopOfStack - This is the new top of the memory stack for ensuing code. This is mandatory and
// should be non-zero
// NewBSPStore - This is the new BSP store for the ensuing code. It is optional on IA-32 and mandatory on Itanium-based platform.
//
//--*/
PROCEDURE_ENTRY(SwitchStack)
mov r16 = -0x10;;
and r16 = r34, r16;; // get new stack value in R16, 0 the last nibble.
mov r15 = r35;; // Get new BspStore into R15
mov r13 = r32;; // this is a pointer to the PLABEL of the continuation function.
mov r17 = r33;; // this is the parameter to pass to the continuation function
alloc r11=0,0,0,0 // Set 0-size frame
;;
flushrs;;
mov r21 = RSC_KERNEL_DISABLED // for rse disable
;;
mov ar.rsc = r21 // turn off RSE
add sp = r0, r16;; // transfer to the EFI stack
mov ar.bspstore = r15 // switch to EFI BSP
invala // change of ar.bspstore needs invala.
mov r18 = RSC_KERNEL_LAZ // RSC enabled, Lazy mode
;;
mov ar.rsc = r18 // turn rse on, in kernel mode
;;
alloc r11=0,0,1,0;; // alloc 0 outs going to ensuing DXE IPL service
mov out0 = r17
ld8 r16 = [r13],8;; // r16 = address of continuation function from the PLABEL
ld8 gp = [r13] // gp = gp of continuation function from the PLABEL
mov b6 = r16
;;
br.call.sptk.few b0=b6;; // Call the continuation function
;;
PROCEDURE_EXIT(SwitchStack)

59
MdePkg/Library/BaseLib/Ipf/Synchronization.c Normal file
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/** @file
Implementation of synchronization functions on Itanium.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Synchronization.c
**/
UINT32
EFIAPI
InternalSyncCompareExchange32 (
IN volatile UINT32 *Value,
IN UINT32 CompareValue,
IN UINT32 ExchangeValue
);
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
UINT32 OriginalValue;
do {
OriginalValue = *Value;
} while (OriginalValue == InternalSyncCompareExchange32 (
Value,
OriginalValue,
OriginalValue + 1
));
return OriginalValue + 1;
}
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
UINT32 OriginalValue;
do {
OriginalValue = *Value;
} while (OriginalValue == InternalSyncCompareExchange32 (
Value,
OriginalValue,
OriginalValue - 1
));
return OriginalValue - 1;
}

220
MdePkg/Library/BaseLib/Ipf/Unaligned.c Normal file
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/** @file
Unaligned access functions of BaseLib for IPF.
Copyright (c) 2006, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Unaligned.c
**/
/**
Reads a 16-bit value from memory that may be unaligned.
This function returns the 16-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@return *Uint16
**/
UINT16
EFIAPI
ReadUnaligned16 (
IN CONST UINT16 *Buffer
)
{
return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));
}
/**
Writes a 16-bit value to memory that may be unaligned.
This function writes the 16-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@param Value 16-bit value to write to Buffer.
@return Value
**/
UINT16
EFIAPI
WriteUnaligned16 (
OUT UINT16 *Buffer,
IN UINT16 Value
)
{
((UINT8*)Buffer)[0] = (UINT8)Value;
((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
return Value;
}
/**
Reads a 24-bit value from memory that may be unaligned.
This function returns the 24-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@return The value read.
**/
UINT32
EFIAPI
ReadUnaligned24 (
IN CONST UINT32 *Buffer
)
{
return (UINT32)(
ReadUnaligned16 ((UINT16*)Buffer) |
(((UINT8*)Buffer)[2] << 16)
);
}
/**
Writes a 24-bit value to memory that may be unaligned.
This function writes the 24-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@param Value 24-bit value to write to Buffer.
@return The value written.
**/
UINT32
EFIAPI
WriteUnaligned24 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
*(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
return Value;
}
/**
Reads a 32-bit value from memory that may be unaligned.
This function returns the 32-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@return *Uint32
**/
UINT32
EFIAPI
ReadUnaligned32 (
IN CONST UINT32 *Buffer
)
{
return (UINT32)(
ReadUnaligned16 ((UINT16*)Buffer) |
(ReadUnaligned16 ((UINT16*)Buffer + 1) << 16)
);
}
/**
Writes a 32-bit value to memory that may be unaligned.
This function writes the 32-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@param Value 32-bit value to write to Buffer.
@return Value
**/
UINT32
EFIAPI
WriteUnaligned32 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
return Value;
}
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return *Uint64
**/
UINT64
EFIAPI
ReadUnaligned64 (
IN CONST UINT64 *Buffer
)
{
return (UINT64)(
ReadUnaligned32 ((UINT32*)Buffer) |
LShiftU64 (ReadUnaligned32 ((UINT32*)Buffer + 1), 32)
);
}
/**
Writes a 64-bit value to memory that may be unaligned.
This function writes the 64-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@param Value 64-bit value to write to Buffer.
@return Value
**/
UINT64
EFIAPI
WriteUnaligned64 (
OUT UINT64 *Buffer,
IN UINT64 Value
)
{
WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
return Value;
}

27
MdePkg/Library/BaseLib/Ipf/asm.h Normal file
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/// @file
/// This module contains generic macros for an assembly writer.
///
/// Copyright (c) 2006, Intel Corporation<BR>
/// All rights reserved. This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: asm.h
///
#ifndef _ASM_H
#define _ASM_H
#define TRUE 1
#define FALSE 0
#define PROCEDURE_ENTRY(name) .##text; \
.##type name, @function; \
.##proc name; \
name::
#define PROCEDURE_EXIT(name) .##endp name
#endif // _ASM_H

205
MdePkg/Library/BaseLib/Ipf/ia_64gen.h Normal file
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/// @file
///
///
/// Copyright (c) 2006, Intel Corporation<BR>
/// All rights reserved. This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: ia_64gen.h
///
#ifndef _IA64GEN_H
#define _IA64GEN_H
#define TT_UNAT 0
#define C_PSR 0
#define J_UNAT 0
#define T_TYPE 0
#define T_IPSR 0x8
#define T_ISR 0x10
#define T_IIP 0x18
#define T_IFA 0x20
#define T_IIPA 0x28
#define T_IFS 0x30
#define T_IIM 0x38
#define T_RSC 0x40
#define T_BSP 0x48
#define T_BSPSTORE 0x50
#define T_RNAT 0x58
#define T_PFS 0x60
#define T_KBSPSTORE 0x68
#define T_UNAT 0x70
#define T_CCV 0x78
#define T_DCR 0x80
#define T_PREDS 0x88
#define T_NATS 0x90
#define T_R1 0x98
#define T_GP 0x98
#define T_R2 0xa0
#define T_R3 0xa8
#define T_R4 0xb0
#define T_R5 0xb8
#define T_R6 0xc0
#define T_R7 0xc8
#define T_R8 0xd0
#define T_R9 0xd8
#define T_R10 0xe0
#define T_R11 0xe8
#define T_R12 0xf0
#define T_SP 0xf0
#define T_R13 0xf8
#define T_R14 0x100
#define T_R15 0x108
#define T_R16 0x110
#define T_R17 0x118
#define T_R18 0x120
#define T_R19 0x128
#define T_R20 0x130
#define T_R21 0x138
#define T_R22 0x140
#define T_R23 0x148
#define T_R24 0x150
#define T_R25 0x158
#define T_R26 0x160
#define T_R27 0x168
#define T_R28 0x170
#define T_R29 0x178
#define T_R30 0x180
#define T_R31 0x188
#define T_F2 0x1f0
#define T_F3 0x200
#define T_F4 0x210
#define T_F5 0x220
#define T_F6 0x230
#define T_F7 0x240
#define T_F8 0x250
#define T_F9 0x260
#define T_F10 0x270
#define T_F11 0x280
#define T_F12 0x290
#define T_F13 0x2a0
#define T_F14 0x2b0
#define T_F15 0x2c0
#define T_F16 0x2d0
#define T_F17 0x2e0
#define T_F18 0x2f0
#define T_F19 0x300
#define T_F20 0x310
#define T_F21 0x320
#define T_F22 0x330
#define T_F23 0x340
#define T_F24 0x350
#define T_F25 0x360
#define T_F26 0x370
#define T_F27 0x380
#define T_F28 0x390
#define T_F29 0x3a0
#define T_F30 0x3b0
#define T_F31 0x3c0
#define T_FPSR 0x1e0
#define T_B0 0x190
#define T_B1 0x198
#define T_B2 0x1a0
#define T_B3 0x1a8
#define T_B4 0x1b0
#define T_B5 0x1b8
#define T_B6 0x1c0
#define T_B7 0x1c8
#define T_EC 0x1d0
#define T_LC 0x1d8
#define J_NATS 0x8
#define J_PFS 0x10
#define J_BSP 0x18
#define J_RNAT 0x20
#define J_PREDS 0x28
#define J_LC 0x30
#define J_R4 0x38
#define J_R5 0x40
#define J_R6 0x48
#define J_R7 0x50
#define J_SP 0x58
#define J_F2 0x60
#define J_F3 0x70
#define J_F4 0x80
#define J_F5 0x90
#define J_F16 0xa0
#define J_F17 0xb0
#define J_F18 0xc0
#define J_F19 0xd0
#define J_F20 0xe0
#define J_F21 0xf0
#define J_F22 0x100
#define J_F23 0x110
#define J_F24 0x120
#define J_F25 0x130
#define J_F26 0x140
#define J_F27 0x150
#define J_F28 0x160
#define J_F29 0x170
#define J_F30 0x180
#define J_F31 0x190
#define J_FPSR 0x1a0
#define J_B0 0x1a8
#define J_B1 0x1b0
#define J_B2 0x1b8
#define J_B3 0x1c0
#define J_B4 0x1c8
#define J_B5 0x1d0
#define TRAP_FRAME_LENGTH 0x3d0
#define C_UNAT 0x28
#define C_NATS 0x30
#define C_PFS 0x8
#define C_BSPSTORE 0x10
#define C_RNAT 0x18
#define C_RSC 0x20
#define C_PREDS 0x38
#define C_LC 0x40
#define C_DCR 0x48
#define C_R1 0x50
#define C_GP 0x50
#define C_R4 0x58
#define C_R5 0x60
#define C_R6 0x68
#define C_R7 0x70
#define C_SP 0x78
#define C_R13 0x80
#define C_F2 0x90
#define C_F3 0xa0
#define C_F4 0xb0
#define C_F5 0xc0
#define C_F16 0xd0
#define C_F17 0xe0
#define C_F18 0xf0
#define C_F19 0x100
#define C_F20 0x110
#define C_F21 0x120
#define C_F22 0x130
#define C_F23 0x140
#define C_F24 0x150
#define C_F25 0x160
#define C_F26 0x170
#define C_F27 0x180
#define C_F28 0x190
#define C_F29 0x1a0
#define C_F30 0x1b0
#define C_F31 0x1c0
#define C_FPSR 0x1d0
#define C_B0 0x1d8
#define C_B1 0x1e0
#define C_B2 0x1e8
#define C_B3 0x1f0
#define C_B4 0x1f8
#define C_B5 0x200
#define TT_R2 0x8
#define TT_R3 0x10
#define TT_R8 0x18
#define TT_R9 0x20
#define TT_R10 0x28
#define TT_R11 0x30
#define TT_R14 0x38
#endif _IA64GEN_H

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MdePkg/Library/BaseLib/Ipf/setjmp.s Normal file
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/// @file
/// Contains an implementation of setjmp and longjmp for the
/// Itanium-based architecture.
///
/// Copyright (c) 2006, Intel Corporation
/// All rights reserved. This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: setjmp.s
///
///
.file "setjmp.s"
#include "asm.h"
#include "ia_64gen.h"
/// int SetJump(struct jmp_buffer save)
///
/// Setup a non-local goto.
///
/// Description:
///
/// SetJump stores the current register set in the area pointed to
/// by "save". It returns zero. Subsequent calls to "LongJump" will
/// restore the registers and return non-zero to the same location.
///
/// On entry, r32 contains the pointer to the jmp_buffer
///
PROCEDURE_ENTRY(SetJump)
//
// Make sure buffer is aligned at 16byte boundary
//
mov r32 = r33
add r10 = -0x10,r0 ;; // mask the lower 4 bits
and r32 = r32, r10;;
add r32 = 0x10, r32;; // move to next 16 byte boundary
add r10 = J_PREDS, r32 // skip Unats & pfs save area
add r11 = J_BSP, r32
//
// save immediate context
//
mov r2 = ar.bsp // save backing store pointer
mov r3 = pr // save predicates
;;
//
// save user Unat register
//
mov r16 = ar.lc // save loop count register
mov r14 = ar.unat // save user Unat register
st8 [r10] = r3, J_LC-J_PREDS
st8 [r11] = r2, J_R4-J_BSP
;;
st8 [r10] = r16, J_R5-J_LC
st8 [r32] = r14, J_NATS // Note: Unat at the
// beginning of the save area
mov r15 = ar.pfs
;;
//
// save preserved general registers & NaT's
//
st8.spill [r11] = r4, J_R6-J_R4
;;
st8.spill [r10] = r5, J_R7-J_R5
;;
st8.spill [r11] = r6, J_SP-J_R6
;;
st8.spill [r10] = r7, J_F3-J_R7
;;
st8.spill [r11] = sp, J_F2-J_SP
;;
//
// save spilled Unat and pfs registers
//
mov r2 = ar.unat // save Unat register after spill
;;
st8 [r32] = r2, J_PFS-J_NATS // save unat for spilled regs
;;
st8 [r32] = r15 // save pfs
//
// save floating registers
//
stf.spill [r11] = f2, J_F4-J_F2
stf.spill [r10] = f3, J_F5-J_F3
;;
stf.spill [r11] = f4, J_F16-J_F4
stf.spill [r10] = f5, J_F17-J_F5
;;
stf.spill [r11] = f16, J_F18-J_F16
stf.spill [r10] = f17, J_F19-J_F17
;;
stf.spill [r11] = f18, J_F20-J_F18
stf.spill [r10] = f19, J_F21-J_F19
;;
stf.spill [r11] = f20, J_F22-J_F20
stf.spill [r10] = f21, J_F23-J_F21
;;
stf.spill [r11] = f22, J_F24-J_F22
stf.spill [r10] = f23, J_F25-J_F23
;;
stf.spill [r11] = f24, J_F26-J_F24
stf.spill [r10] = f25, J_F27-J_F25
;;
stf.spill [r11] = f26, J_F28-J_F26
stf.spill [r10] = f27, J_F29-J_F27
;;
stf.spill [r11] = f28, J_F30-J_F28
stf.spill [r10] = f29, J_F31-J_F29
;;
stf.spill [r11] = f30, J_FPSR-J_F30
stf.spill [r10] = f31, J_B0-J_F31 // size of f31 + fpsr
//
// save FPSR register & branch registers
//
mov r2 = ar.fpsr // save fpsr register
mov r3 = b0
;;
st8 [r11] = r2, J_B1-J_FPSR
st8 [r10] = r3, J_B2-J_B0
mov r2 = b1
mov r3 = b2
;;
st8 [r11] = r2, J_B3-J_B1
st8 [r10] = r3, J_B4-J_B2
mov r2 = b3
mov r3 = b4
;;
st8 [r11] = r2, J_B5-J_B3
st8 [r10] = r3
mov r2 = b5
;;
st8 [r11] = r2
;;
//
// return
//
mov r8 = r0 // return 0 from setjmp
mov ar.unat = r14 // restore unat
br.ret.sptk b0
PROCEDURE_EXIT(SetJump)
//
// void LongJump(struct jmp_buffer *)
//
// Perform a non-local goto.
//
// Description:
//
// LongJump initializes the register set to the values saved by a
// previous 'SetJump' and jumps to the return location saved by that
// 'SetJump'. This has the effect of unwinding the stack and returning
// for a second time to the 'SetJump'.
//
PROCEDURE_ENTRY(LongJump)
//
// Make sure buffer is aligned at 16byte boundary
//
mov r32 = r33
add r10 = -0x10,r0 ;; // mask the lower 4 bits
and r32 = r32, r10;;
add r32 = 0x10, r32;; // move to next 16 byte boundary
//
// caching the return value as we do invala in the end
//
/// mov r8 = r33 // return value
mov r8 = 1 // For now return hard coded 1
//
// get immediate context
//
mov r14 = ar.rsc // get user RSC conf
add r10 = J_PFS, r32 // get address of pfs
add r11 = J_NATS, r32
;;
ld8 r15 = [r10], J_BSP-J_PFS // get pfs
ld8 r2 = [r11], J_LC-J_NATS // get unat for spilled regs
;;
mov ar.unat = r2
;;
ld8 r16 = [r10], J_PREDS-J_BSP // get backing store pointer
mov ar.rsc = r0 // put RSE in enforced lazy
mov ar.pfs = r15
;;
//
// while returning from longjmp the BSPSTORE and BSP needs to be
// same and discard all the registers allocated after we did
// setjmp. Also, we need to generate the RNAT register since we
// did not flushed the RSE on setjmp.
//
mov r17 = ar.bspstore // get current BSPSTORE
;;
cmp.ltu p6,p7 = r17, r16 // is it less than BSP of
(p6) br.spnt.few .flush_rse
mov r19 = ar.rnat // get current RNAT
;;
loadrs // invalidate dirty regs
br.sptk.many .restore_rnat // restore RNAT
.flush_rse:
flushrs
;;
mov r19 = ar.rnat // get current RNAT
mov r17 = r16 // current BSPSTORE
;;
.restore_rnat:
//
// check if RNAT is saved between saved BSP and curr BSPSTORE
//
dep r18 = 1,r16,3,6 // get RNAT address
;;
cmp.ltu p8,p9 = r18, r17 // RNAT saved on RSE
;;
(p8) ld8 r19 = [r18] // get RNAT from RSE
;;
mov ar.bspstore = r16 // set new BSPSTORE
;;
mov ar.rnat = r19 // restore RNAT
mov ar.rsc = r14 // restore RSC conf
ld8 r3 = [r11], J_R4-J_LC // get lc register
ld8 r2 = [r10], J_R5-J_PREDS // get predicates
;;
mov pr = r2, -1
mov ar.lc = r3
//
// restore preserved general registers & NaT's
//
ld8.fill r4 = [r11], J_R6-J_R4
;;
ld8.fill r5 = [r10], J_R7-J_R5
ld8.fill r6 = [r11], J_SP-J_R6
;;
ld8.fill r7 = [r10], J_F2-J_R7
ld8.fill sp = [r11], J_F3-J_SP
;;
//
// restore floating registers
//
ldf.fill f2 = [r10], J_F4-J_F2
ldf.fill f3 = [r11], J_F5-J_F3
;;
ldf.fill f4 = [r10], J_F16-J_F4
ldf.fill f5 = [r11], J_F17-J_F5
;;
ldf.fill f16 = [r10], J_F18-J_F16
ldf.fill f17 = [r11], J_F19-J_F17
;;
ldf.fill f18 = [r10], J_F20-J_F18
ldf.fill f19 = [r11], J_F21-J_F19
;;
ldf.fill f20 = [r10], J_F22-J_F20
ldf.fill f21 = [r11], J_F23-J_F21
;;
ldf.fill f22 = [r10], J_F24-J_F22
ldf.fill f23 = [r11], J_F25-J_F23
;;
ldf.fill f24 = [r10], J_F26-J_F24
ldf.fill f25 = [r11], J_F27-J_F25
;;
ldf.fill f26 = [r10], J_F28-J_F26
ldf.fill f27 = [r11], J_F29-J_F27
;;
ldf.fill f28 = [r10], J_F30-J_F28
ldf.fill f29 = [r11], J_F31-J_F29
;;
ldf.fill f30 = [r10], J_FPSR-J_F30
ldf.fill f31 = [r11], J_B0-J_F31 ;;
//
// restore branch registers and fpsr
//
ld8 r16 = [r10], J_B1-J_FPSR // get fpsr
ld8 r17 = [r11], J_B2-J_B0 // get return pointer
;;
mov ar.fpsr = r16
mov b0 = r17
ld8 r2 = [r10], J_B3-J_B1
ld8 r3 = [r11], J_B4-J_B2
;;
mov b1 = r2
mov b2 = r3
ld8 r2 = [r10], J_B5-J_B3
ld8 r3 = [r11]
;;
mov b3 = r2
mov b4 = r3
ld8 r2 = [r10]
ld8 r21 = [r32] // get user unat
;;
mov b5 = r2
mov ar.unat = r21
//
// invalidate ALAT
//
invala ;;
br.ret.sptk b0
PROCEDURE_EXIT(LongJump)