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UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default

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So that we can use write-protection for code later.

This is REPOST.
It includes the bug fix from "Paolo Bonzini" <pbonzini@redhat.com>:

  Title: fix generation of 32-bit PAE page tables

  "Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table
  Entries (PDPTEs); see Table 4-8 in the SDM.  With VMX extended page
  tables, the processor notices and fails the VM entry as soon as CR0.PG
  is set to 1."

And thanks "Laszlo Ersek" <lersek@redhat.com> to validate the fix.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Signed-off-by: "Paolo Bonzini" <pbonzini@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Yao, Jiewen
2015-11-30 19:57:40 +00:00
committed by lersek
parent 5e04f4b7e1
commit 881520ea67
7 changed files with 39 additions and 26 deletions
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13
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
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@@ -71,15 +71,24 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
#define IA32_PG_P BIT0
#define IA32_PG_RW BIT1
#define IA32_PG_U BIT2
#define IA32_PG_WT BIT3
#define IA32_PG_CD BIT4
#define IA32_PG_A BIT5
#define IA32_PG_D BIT6
#define IA32_PG_PS BIT7
#define IA32_PG_PAT_2M BIT12
#define IA32_PG_PAT_4K IA32_PG_PS
#define IA32_PG_PMNT BIT62
#define IA32_PG_NX BIT63
#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)
//
// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
// X64 PAE PDPTE does not have such restriction
//
#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)
//
// Size of Task-State Segment defined in IA32 Manual
//
@@ -364,12 +373,14 @@ extern IA32_DESCRIPTOR gcSmiInitGdtr;
Create 4G PageTable in SMRAM.
@param ExtraPages Additional page numbers besides for 4G memory
@param Is32BitPageTable Whether the page table is 32-bit PAE
@return PageTable Address
**/
UINT32
Gen4GPageTable (
IN UINTN ExtraPages
IN UINTN ExtraPages,
IN BOOLEAN Is32BitPageTable
);