UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default
So that we can use write-protection for code later. This is REPOST. It includes the bug fix from "Paolo Bonzini" <pbonzini@redhat.com>: Title: fix generation of 32-bit PAE page tables "Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table Entries (PDPTEs); see Table 4-8 in the SDM. With VMX extended page tables, the processor notices and fails the VM entry as soon as CR0.PG is set to 1." And thanks "Laszlo Ersek" <lersek@redhat.com> to validate the fix. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Signed-off-by: "Paolo Bonzini" <pbonzini@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> Cc: "Paolo Bonzini" <pbonzini@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -557,9 +557,9 @@ InitPaging (
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// Split it
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for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {
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Pt[Level4] = Address + ((Level4 << 12) | IA32_PG_RW | IA32_PG_P);
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Pt[Level4] = Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS);
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} // end for PT
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*Pte = (UINTN)Pt | IA32_PG_RW | IA32_PG_P;
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*Pte = (UINTN)Pt | PAGE_ATTRIBUTE_BITS;
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} // end if IsAddressSplit
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} // end for PTE
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} // end for PDE
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@@ -608,7 +608,7 @@ InitPaging (
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//
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// Patch to remove Present flag and RW flag
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//
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*Pte = *Pte & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));
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*Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
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}
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if (Nx && mXdSupported) {
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*Pte = *Pte | IA32_PG_NX;
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@@ -621,7 +621,7 @@ InitPaging (
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}
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for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {
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if (!IsAddressValid (Address, &Nx)) {
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*Pt = *Pt & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));
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*Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
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}
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if (Nx && mXdSupported) {
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*Pt = *Pt | IA32_PG_NX;
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@@ -1244,7 +1244,7 @@ RestorePageTableBelow4G (
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//
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PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));
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PageTable[PTIndex] |= (UINT64)IA32_PG_PS;
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PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);
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PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
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if ((ErrorCode & IA32_PF_EC_ID) != 0) {
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PageTable[PTIndex] &= ~IA32_PG_NX;
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}
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@@ -1277,7 +1277,7 @@ RestorePageTableBelow4G (
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// Set new entry
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//
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PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));
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PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);
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PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
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if ((ErrorCode & IA32_PF_EC_ID) != 0) {
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PageTable[PTIndex] &= ~IA32_PG_NX;
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}
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