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ARM Packages: Fixed Build failings/warnings/EDK2 coding convention

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12458 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-09-27 16:42:47 +00:00
parent 12fcdcb83d
commit 886f97c86b
21 changed files with 56 additions and 103 deletions
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2
ArmPkg/Drivers/CpuDxe/CpuDxe.c
View File

@@ -259,7 +259,7 @@ CpuDxeInitialize (
// If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states
if (ArmIsMPCore()) {
if (ArmIsMpCore()) {
PublishArmProcessorTable();
}

4
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
View File

@@ -27,7 +27,7 @@ ArmGicEnableInterruptInterface (
* Enable the CPU interface in Non-Secure world
* Note: The ICCICR register is banked when Security extensions are implemented
*/
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001);
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
}
VOID
@@ -40,5 +40,5 @@ ArmGicEnableDistributor (
* Enable GIC distributor in Non-Secure world.
* Note: The ICDDCR register is banked when Security extensions are implemented
*/
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001);
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
}

37
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@@ -27,28 +27,31 @@ ArmGicSetupNonSecure (
IN INTN GicInterruptInterfaceBase
)
{
UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
UINTN InterruptId;
UINTN CachedPriorityMask;
CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
// Set priority Mask so that no interrupts get through to CPU
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
// Check if there are any pending interrupts
//TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Write to End of interrupt signal
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
}
// Ensure all GIC interrupts are Non-Secure
MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
// Ensure all interrupts can get through the priority mask
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
}
VOID
@@ -57,14 +60,13 @@ ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
)
{
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
// Set Priority Mask to allow interrupts
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
/*
* Enable CPU interface in Secure world
* Enable CPU inteface in Non-secure World
* Signal Secure Interrupts to CPU using FIQ line *
*/
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
// Enable CPU interface in Secure world
// Enable CPU inteface in Non-secure World
// Signal Secure Interrupts to CPU using FIQ line *
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
ARM_GIC_ICCICR_ENABLE_SECURE |
ARM_GIC_ICCICR_ENABLE_NS |
ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
@@ -76,5 +78,6 @@ ArmGicEnableDistributor (
IN INTN GicDistributorBase
)
{
MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor
// Turn on the GIC distributor
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
}