ArmPlatformPkg: Add support for ARM RTSM Versatile Express A15x1 and A15x4
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12456 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmV7.h>
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.text
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.align 3
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GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
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GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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// Dirty hack to get the Fixed value of GicDistributorBase
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GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdGicDistributorBase)
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitGicDistributorEnabled
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b CArmCpuSynchronizeWait
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// IN None
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ArmWaitGicDistributorEnabled:
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LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
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ldr r0, [r0]
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_WaitGicDistributor:
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ldr r1, [r0, #ARM_GIC_ICDDCR]
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cmp r1, #1
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bne _WaitGicDistributor
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bx lr
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@@ -0,0 +1,50 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmV7.h>
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmCpuSynchronizeWait
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IMPORT CArmCpuSynchronizeWait
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// Dirty hack to get the Fixed value of GicDistributorBase
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IMPORT _gPcd_FixedAtBuild_PcdGicDistributorBase
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PRESERVE8
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AREA ArmCortexA15Helper, CODE, READONLY
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ArmCpuSynchronizeWait
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitGicDistributorEnabled
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b CArmCpuSynchronizeWait
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// IN None
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ArmWaitGicDistributorEnabled
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LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
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ldr r0, [r0]
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_WaitGicDistributor
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ldr r1, [r0, #ARM_GIC_ICDDCR]
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cmp r1, #1
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bne _WaitGicDistributor
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bx lr
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END
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95
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
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95
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
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/** @file
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Copyright (c) 2011, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/ArmV7ArchTimerLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmV7.h>
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VOID
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ArmCpuSynchronizeSignal (
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IN ARM_CPU_SYNCHRONIZE_EVENT Event
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)
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{
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if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
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// Do nothing, Cortex A15 secondary cores are waiting for the GIC Distributor
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// to be enabled (done by the Sec module itself) as a way to know when the Init Boot
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// Mem as been initialized
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} else {
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// Send SGI to all Secondary core to wake them up from WFI state.
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ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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}
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VOID
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CArmCpuSynchronizeWait (
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IN ARM_CPU_SYNCHRONIZE_EVENT Event
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)
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{
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// Waiting for the SGI from the primary core
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ArmCallWFI ();
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
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}
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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// Check if Architectural Timer frequency is valid number (should not be 0)
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ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
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ASSERT(ArmIsArchTimerImplemented () != 0);
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// Enable SWP instructions
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ArmEnableSWPInstruction ();
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction ();
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// Note: System Counter frequency can only be set in Secure privileged mode,
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// if security extensions are implemented.
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ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
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/*// If MPCore then Enable the SCU
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if (ArmIsMpCore()) {
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ArmEnableScu ();
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}*/
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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//ArmSetAuxCrBit (A15_FEATURE_SMP);
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/*// Make the SCU accessible in Non Secure world
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if (IS_PRIMARY_CORE(MpId)) {
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ScuBase = ArmGetScuBaseAddress();
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// Allow NS access to SCU register
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MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
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// Allow NS access to Private Peripherals
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MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
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}*/
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}
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46
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
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46
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
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@@ -0,0 +1,46 @@
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = ArmCortexA15Lib
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FILE_GUID = 501b1c8f-21d5-4ef5-a565-435b7f0aae2d
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmCpuLib
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[Packages]
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MdePkg/MdePkg.dec
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ArmPkg/ArmPkg.dec
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[LibraryClasses]
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ArmLib
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ArmGicSecLib
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IoLib
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PcdLib
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[Sources.common]
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ArmCortexA15Lib.c
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ArmCortexA15Helper.asm | RVCT
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ArmCortexA15Helper.S | GCC
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[FeaturePcd]
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
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