ArmPlatformPkg: Add support for ARM RTSM Versatile Express A15x1 and A15x4

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12456 6f19259b-4bc3-4df7-8a09-765794883524

ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.S

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+//
+//  Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmCpuLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/PcdLib.h>
+#include <Chipset/ArmV7.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
+GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
+// Dirty hack to get the Fixed value of GicDistributorBase
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdGicDistributorBase)
+
+
+// VOID
+// ArmCpuSynchronizeWait (
+//   IN ARM_CPU_SYNCHRONIZE_EVENT   Event
+//   );
+ASM_PFX(ArmCpuSynchronizeWait):
+  cmp   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
+  // The SCU enabled is the event to tell us the Init Boot Memory is initialized
+  beq   ArmWaitGicDistributorEnabled
+  b     CArmCpuSynchronizeWait
+
+// IN  None
+ArmWaitGicDistributorEnabled:
+  LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
+  ldr   r0, [r0]
+_WaitGicDistributor:
+  ldr   r1, [r0, #ARM_GIC_ICDDCR]
+  cmp   r1, #1
+  bne   _WaitGicDistributor
+  bx    lr

ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.asm

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+//
+//  Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmCpuLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/PcdLib.h>
+#include <Chipset/ArmV7.h>
+
+  INCLUDE AsmMacroIoLib.inc
+
+  EXPORT  ArmCpuSynchronizeWait
+  IMPORT  CArmCpuSynchronizeWait
+  // Dirty hack to get the Fixed value of GicDistributorBase
+  IMPORT  _gPcd_FixedAtBuild_PcdGicDistributorBase
+
+  PRESERVE8
+  AREA    ArmCortexA15Helper, CODE, READONLY
+
+// VOID
+// ArmCpuSynchronizeWait (
+//   IN ARM_CPU_SYNCHRONIZE_EVENT   Event
+//   );
+ArmCpuSynchronizeWait
+  cmp   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
+  // The SCU enabled is the event to tell us the Init Boot Memory is initialized
+  beq   ArmWaitGicDistributorEnabled
+  b     CArmCpuSynchronizeWait
+
+// IN  None
+ArmWaitGicDistributorEnabled
+  LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
+  ldr   r0, [r0]
+_WaitGicDistributor
+  ldr   r1, [r0, #ARM_GIC_ICDDCR]
+  cmp   r1, #1
+  bne   _WaitGicDistributor
+  bx    lr
+
+  END

ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c

@@ -0,0 +1,95 @@
+/** @file
+
+  Copyright (c) 2011, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmCpuLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/ArmV7ArchTimerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include <Chipset/ArmV7.h>
+
+VOID
+ArmCpuSynchronizeSignal (
+  IN ARM_CPU_SYNCHRONIZE_EVENT   Event
+  )
+{
+  if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
+    // Do nothing, Cortex A15 secondary cores are waiting for the GIC Distributor
+    // to be enabled (done by the Sec module itself) as a way to know when the Init Boot
+    // Mem as been initialized
+  } else {
+    // Send SGI to all Secondary core to wake them up from WFI state.
+    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+  }
+}
+
+VOID
+CArmCpuSynchronizeWait (
+  IN ARM_CPU_SYNCHRONIZE_EVENT   Event
+  )
+{
+  // Waiting for the SGI from the primary core
+  ArmCallWFI ();
+
+  // Acknowledge the interrupt and send End of Interrupt signal.
+  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
+}
+
+VOID
+ArmCpuSetup (
+  IN  UINTN         MpId
+  )
+{
+  // Check if Architectural Timer frequency is valid number (should not be 0)
+  ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
+  ASSERT(ArmIsArchTimerImplemented () != 0);
+
+  // Enable SWP instructions
+  ArmEnableSWPInstruction ();
+
+  // Enable program flow prediction, if supported.
+  ArmEnableBranchPrediction ();
+
+  // Note: System Counter frequency can only be set in Secure privileged mode,
+  // if security extensions are implemented.
+  ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
+
+  /*// If MPCore then Enable the SCU
+  if (ArmIsMpCore()) {
+    ArmEnableScu ();
+  }*/
+}
+
+
+VOID
+ArmCpuSetupSmpNonSecure (
+  IN  UINTN         MpId
+  )
+{
+  //ArmSetAuxCrBit (A15_FEATURE_SMP);
+
+  /*// Make the SCU accessible in Non Secure world
+  if (IS_PRIMARY_CORE(MpId)) {
+    ScuBase = ArmGetScuBaseAddress();
+
+    // Allow NS access to SCU register
+    MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
+    // Allow NS access to Private Peripherals
+    MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
+  }*/
+}

ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf

@@ -0,0 +1,46 @@
+#/* @file
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmCortexA15Lib
+  FILE_GUID                      = 501b1c8f-21d5-4ef5-a565-435b7f0aae2d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmCpuLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  ArmGicSecLib
+  IoLib
+  PcdLib
+
+[Sources.common]
+  ArmCortexA15Lib.c
+  ArmCortexA15Helper.asm     | RVCT
+  ArmCortexA15Helper.S       | GCC
+
+[FeaturePcd]
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz