Arm Packages: Fix builds for XCODE32 toolchain
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12509 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -27,7 +27,7 @@ ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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bx lr
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b CArmCpuSynchronizeWait
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b ASM_PFX(CArmCpuSynchronizeWait)
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#if 0
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@@ -43,7 +43,7 @@ ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitScuEnabled
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b CArmCpuSynchronizeWait
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b ASM_PFX(CArmCpuSynchronizeWait)
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// IN None
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// OUT r0 = SCU Base Address
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@@ -34,11 +34,11 @@ ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitGicDistributorEnabled
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b CArmCpuSynchronizeWait
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bx ASM_PFX(CArmCpuSynchronizeWait)
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// IN None
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ArmWaitGicDistributorEnabled:
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LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
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LoadConstantToReg (ASM_PFX(_gPcd_FixedAtBuild_PcdGicDistributorBase), r0)
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ldr r0, [r0]
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_WaitGicDistributor:
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ldr r1, [r0, #ARM_GIC_ICDDCR]
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@@ -28,8 +28,8 @@ GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitScuEnabled
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b CArmCpuSynchronizeWait
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beq ASM_PFX(ArmWaitScuEnabled)
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b ASM_PFX(CArmCpuSynchronizeWait)
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// IN None
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// OUT r0 = SCU Base Address
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@@ -48,5 +48,5 @@ ASM_PFX(ArmWaitScuEnabled):
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add r0, r0, #A9_SCU_CONTROL_OFFSET
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ldr r0, [r0]
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cmp r0, #1
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bne ArmWaitScuEnabled
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bne ASM_PFX(ArmWaitScuEnabled)
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bx lr
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@@ -119,6 +119,21 @@
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.long (_Data) ; \
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1:
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// Convert the (ClusterId,CoreId) into a Core Position
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// We assume there are 4 cores per cluster
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#define GetCorePositionInStack(Pos, MpId, Tmp) \
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lsr Pos, MpId, #6 ; \
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and Tmp, MpId, #3 ; \
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add Pos, Pos, Tmp
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// Reserve a region at the top of the Primary Core stack
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// for Global variables for the XIP phase
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#define SetPrimaryStack(StackTop, GlobalSize, Tmp) \
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and Tmp, GlobalSize, #7 ; \
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rsbne Tmp, Tmp, #8 ; \
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add GlobalSize, GlobalSize, Tmp ; \
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sub sp, StackTop, GlobalSize
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#elif defined (__GNUC__)
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@@ -184,7 +184,7 @@ GetPerformanceCounterProperties (
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if (EndValue != NULL) {
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// Timer counts down to 0x0
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*EndValue = 0xFFFFFFFFFFFFFFFF;;
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*EndValue = 0xFFFFFFFFFFFFFFFFUL;
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}
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return (UINT64)ArmArchTimerGetTimerFreq ();
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