IntelFsp2Pkg: Add FSP*_ARCH_UPD.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781 Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events and multi-phase silicon initialization. For backward compatibility the original structures are kept and new ARCH_UPD structures will be included only when UPD header revision equal or greater than 2. GenCfgOpt script also updated to prevent from generating duplicate FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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Chasel Chiu
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mergify[bot]
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00b8bf7eda
commit
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@@ -1,7 +1,7 @@
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;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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@@ -78,6 +78,23 @@ struc LoadMicrocodeParams
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.size:
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endstruc
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struc LoadMicrocodeParamsFsp22
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; FSP_UPD_HEADER {
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.FspUpdHeaderSignature: resd 2
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.FspUpdHeaderRevision: resb 1
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.FspUpdHeaderReserved: resb 23
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; }
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; FSPT_ARCH_UPD{
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.FsptArchUpd: resd 8
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; }
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; FSPT_CORE_UPD {
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.MicrocodeCodeAddr: resd 1
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.MicrocodeCodeSize: resd 1
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.CodeRegionBase: resd 1
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.CodeRegionSize: resd 1
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; }
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.size:
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endstruc
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;
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; Define SSE macros
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@@ -169,6 +186,11 @@ ASM_PFX(LoadMicrocodeDefault):
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; skip loading Microcode if the MicrocodeCodeSize is zero
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; and report error if size is less than 2k
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; first check UPD header revision
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cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
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jae Fsp22UpdHeader
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; UPD structure is compliant with FSP spec 2.0/2.1
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mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
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cmp eax, 0
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jz Exit2
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@@ -178,6 +200,19 @@ ASM_PFX(LoadMicrocodeDefault):
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mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
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cmp esi, 0
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jnz CheckMainHeader
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jmp ParamError
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Fsp22UpdHeader:
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; UPD structure is compliant with FSP spec 2.2
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mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]
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cmp eax, 0
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jz Exit2
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cmp eax, 0800h
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jl ParamError
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mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
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cmp esi, 0
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jnz CheckMainHeader
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ParamError:
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mov eax, 080000002h
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@@ -276,6 +311,11 @@ CheckAddress:
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cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
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jz Done
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; Check UPD header revision
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cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
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jae Fsp22UpdHeader1
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; UPD structure is compliant with FSP spec 2.0/2.1
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; Is automatic size detection ?
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mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
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cmp eax, 0ffffffffh
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@@ -287,6 +327,19 @@ CheckAddress:
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jae Done ;Jif address is outside of microcode region
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jmp CheckMainHeader
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Fsp22UpdHeader1:
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; UPD structure is compliant with FSP spec 2.2
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; Is automatic size detection ?
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mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]
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cmp eax, 0ffffffffh
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jz LoadMicrocodeDefault4
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; Address >= microcode region address + microcode region size?
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add eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
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cmp esi, eax
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jae Done ;Jif address is outside of microcode region
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jmp CheckMainHeader
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LoadMicrocodeDefault4:
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LoadCheck:
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; Get the revision of the current microcode update loaded
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@@ -349,11 +402,26 @@ ASM_PFX(EstablishStackFsp):
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push DATA_LEN_OF_MCUD ; Size of the data region
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push 4455434Dh ; Signature of the data region 'MCUD'
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push dword [edx + 2Ch] ; Code size sizeof(FSPT_UPD_COMMON) + 12
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push dword [edx + 28h] ; Code base sizeof(FSPT_UPD_COMMON) + 8
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push dword [edx + 24h] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
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push dword [edx + 20h] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
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; check UPD structure revision (edx + 8)
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cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
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jae Fsp22UpdHeader2
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; UPD structure is compliant with FSP spec 2.0/2.1
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push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12
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push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
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push dword [edx + LoadMicrocodeParams.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
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push dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
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jmp ContinueAfterUpdPush
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Fsp22UpdHeader2:
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; UPD structure is compliant with FSP spec 2.2
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push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12
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push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
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push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
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push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
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ContinueAfterUpdPush:
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;
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; Save API entry/exit timestamp into stack
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;
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