IntelFsp2Pkg: Add FSP*_ARCH_UPD.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781 Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events and multi-phase silicon initialization. For backward compatibility the original structures are kept and new ARCH_UPD structures will be included only when UPD header revision equal or greater than 2. GenCfgOpt script also updated to prevent from generating duplicate FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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@@ -1175,7 +1175,7 @@ EndList
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UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION
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UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG
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UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE']
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ExcludedSpecificUpd = 'FSPM_ARCH_UPD'
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ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD']
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if InputHeaderFile != '':
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if not os.path.exists(InputHeaderFile):
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@@ -1229,7 +1229,7 @@ EndList
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if Match:
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StartIndex = Index - 1
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Match = re.match("}\s([_A-Z0-9]+);", Line)
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if Match and (UpdRegionCheck[item] in Match.group(1) or UpdConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd not in Match.group(1)):
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if Match and (UpdRegionCheck[item] in Match.group(1) or UpdConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd[item] not in Match.group(1)):
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EndIndex = Index
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StructStart.append(StartIndex)
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StructEnd.append(EndIndex)
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@@ -1466,7 +1466,7 @@ EndList
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def Usage():
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print ("GenCfgOpt Version 0.54")
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print ("GenCfgOpt Version 0.55")
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print ("Usage:")
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print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir [-D Macros]")
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print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile [-D Macros]")
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