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BaseTools: Remove unused logic from C tools

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https://bugzilla.tianocore.org/show_bug.cgi?id=1350
Remove IA64 support from BaseTools C code.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
This commit is contained in:
Feng, Bob C
2019-01-09 16:34:29 +08:00
parent 39879ef267
commit 8daa4278e8
11 changed files with 10 additions and 353 deletions
Download Patch File Download Diff File Expand all files Collapse all files

162
BaseTools/Source/C/Common/PeCoffLoaderEx.c
View File

@@ -1,5 +1,5 @@
/** @file
IA32, X64 and IPF Specific relocation fixups
IA32 and X64 Specific relocation fixups
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
@@ -99,166 +99,6 @@ Returns:
return RETURN_UNSUPPORTED;
}
RETURN_STATUS
PeCoffLoaderRelocateIpfImage (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
/*++
Routine Description:
Performs an Itanium-based specific relocation fixup
Arguments:
Reloc - Pointer to the relocation record
Fixup - Pointer to the address to fix up
FixupData - Pointer to a buffer to log the fixups
Adjust - The offset to adjust the fixup
Returns:
Status code
--*/
{
UINT64 *F64;
UINT64 FixupVal;
switch ((*Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_IA64_IMM64:
//
// Align it to bundle address before fixing up the
// 64-bit immediate value of the movl instruction.
//
Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
FixupVal = (UINT64)0;
//
// Extract the lower 32 bits of IMM64 from bundle
//
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
//
// Update 64-bit address
//
FixupVal += Adjust;
//
// Insert IMM64 into bundle
//
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),
IMM64_IMM41b_SIZE_X,
IMM64_IMM41b_INST_WORD_POS_X,
IMM64_IMM41b_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),
IMM64_IMM41c_SIZE_X,
IMM64_IMM41c_INST_WORD_POS_X,
IMM64_IMM41c_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
IMM64_SIGN_SIZE_X,
IMM64_SIGN_INST_WORD_POS_X,
IMM64_SIGN_VAL_POS_X
);
F64 = (UINT64 *) Fixup;
if (*FixupData != NULL) {
*FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
*(UINT64 *)(*FixupData) = *F64;
*FixupData = *FixupData + sizeof(UINT64);
}
break;
default:
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}
/**
Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and