Print resource allocation/bar programming when PciBus driver does PCI BUS enumeration.
Signed-off-by: niruiyu Reviewed-by: rsun3 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12087 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
niruiyu
parent
48c0731857
commit
8db6a82c50
@ -1,7 +1,7 @@
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/** @file
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/** @file
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Header files and data structures needed by PCI Bus module.
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Header files and data structures needed by PCI Bus module.
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Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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which accompanies this distribution. The full text of the license may be found at
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@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include <Protocol/IncompatiblePciDeviceSupport.h>
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#include <Protocol/IncompatiblePciDeviceSupport.h>
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#include <Protocol/PciOverride.h>
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#include <Protocol/PciOverride.h>
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#include <Protocol/PciEnumerationComplete.h>
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#include <Protocol/PciEnumerationComplete.h>
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#include <Protocol/DevicePathToText.h>
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#include <Library/DebugLib.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiDriverEntryPoint.h>
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#include <Library/UefiDriverEntryPoint.h>
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@ -127,6 +128,12 @@ struct _PCI_BAR {
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#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
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#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
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#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
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#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
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#define RB_IO_RANGE 1
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#define RB_MEM32_RANGE 2
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#define RB_PMEM32_RANGE 3
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#define RB_MEM64_RANGE 4
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#define RB_PMEM64_RANGE 5
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#define PPB_BAR_0 0
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#define PPB_BAR_0 0
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#define PPB_BAR_1 1
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#define PPB_BAR_1 1
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#define PPB_IO_RANGE 2
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#define PPB_IO_RANGE 2
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@ -5,7 +5,7 @@
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# space for these devices. Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable
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# space for these devices. Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable
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# hot plug supporting.
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# hot plug supporting.
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#
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#
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# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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#
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#
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# This program and the accompanying materials
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# are licensed and made available under the terms and conditions of the BSD License
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@ -97,6 +97,7 @@
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gEfiPciRootBridgeIoProtocolGuid ## CONSUMED
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gEfiPciRootBridgeIoProtocolGuid ## CONSUMED
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gEfiIncompatiblePciDeviceSupportProtocolGuid ## CONSUMED
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gEfiIncompatiblePciDeviceSupportProtocolGuid ## CONSUMED
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gEfiLoadFile2ProtocolGuid ## CONSUMED
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gEfiLoadFile2ProtocolGuid ## CONSUMED
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gEfiDevicePathToTextProtocolGuid ## CONSUMED
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[FeaturePcd]
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[FeaturePcd]
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport
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@ -1,7 +1,7 @@
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/** @file
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/** @file
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PCI emumeration support functions implementation for PCI Bus module.
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PCI emumeration support functions implementation for PCI Bus module.
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Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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which accompanies this distribution. The full text of the license may be found at
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@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include "PciBus.h"
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#include "PciBus.h"
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extern CHAR16 *mBarTypeStr[];
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/**
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/**
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This routine is used to check whether the pci device is present.
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This routine is used to check whether the pci device is present.
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@ -211,6 +213,15 @@ PciSearchDevice (
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PciIoDevice = NULL;
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PciIoDevice = NULL;
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DEBUG ((
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EFI_D_INFO,
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"PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
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IS_PCI_BRIDGE (Pci) ? L"PPB" :
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IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :
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L"PCI",
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Bus, Device, Func
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));
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if (!IS_PCI_BRIDGE (Pci)) {
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if (!IS_PCI_BRIDGE (Pci)) {
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if (IS_CARDBUS_BRIDGE (Pci)) {
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if (IS_CARDBUS_BRIDGE (Pci)) {
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@ -304,6 +315,46 @@ PciSearchDevice (
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return EFI_SUCCESS;
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return EFI_SUCCESS;
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}
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}
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/**
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Dump the PCI BAR information.
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@param PciIoDevice PCI IO instance.
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**/
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VOID
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DumpPciBars (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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{
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UINTN Index;
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for (Index = 0; Index < PCI_MAX_BAR; Index++) {
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if (PciIoDevice->PciBar[Index].BarType == PciBarTypeUnknown) {
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continue;
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}
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DEBUG ((
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EFI_D_INFO,
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" BAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",
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Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
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PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset
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));
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}
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for (Index = 0; Index < PCI_MAX_BAR; Index++) {
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if ((PciIoDevice->VfPciBar[Index].BarType == PciBarTypeUnknown) && (PciIoDevice->VfPciBar[Index].Length == 0)) {
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continue;
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}
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DEBUG ((
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EFI_D_INFO,
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" VFBAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",
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Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
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PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
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));
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}
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DEBUG ((EFI_D_INFO, "\n"));
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}
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/**
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/**
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Create PCI device instance for PCI device.
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Create PCI device instance for PCI device.
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@ -377,6 +428,8 @@ GatherDeviceInfo (
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Offset = PciIovParseVfBar (PciIoDevice, Offset, BarIndex);
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Offset = PciIovParseVfBar (PciIoDevice, Offset, BarIndex);
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}
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}
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}
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}
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DEBUG_CODE (DumpPciBars (PciIoDevice););
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return PciIoDevice;
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return PciIoDevice;
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}
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}
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@ -529,6 +582,8 @@ GatherPpbInfo (
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GetResourcePaddingPpb (PciIoDevice);
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GetResourcePaddingPpb (PciIoDevice);
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DEBUG_CODE (DumpPciBars (PciIoDevice););
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return PciIoDevice;
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return PciIoDevice;
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}
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}
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@ -598,6 +653,8 @@ GatherP2CInfo (
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EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
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EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
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EFI_BRIDGE_IO32_DECODE_SUPPORTED;
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EFI_BRIDGE_IO32_DECODE_SUPPORTED;
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DEBUG_CODE (DumpPciBars (PciIoDevice););
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return PciIoDevice;
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return PciIoDevice;
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}
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}
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@ -2035,22 +2092,15 @@ CreatePciIoDevice (
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);
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);
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DEBUG ((
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DEBUG ((
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EFI_D_INFO,
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EFI_D_INFO,
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"PCI B%x.D%x.F%x - ARI forwarding enabled\n",
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" ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
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(UINTN)Bridge->BusNumber,
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Bridge->BusNumber,
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(UINTN)Bridge->DeviceNumber,
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Bridge->DeviceNumber,
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(UINTN)Bridge->FunctionNumber
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Bridge->FunctionNumber
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));
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));
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}
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}
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}
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}
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DEBUG ((
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DEBUG ((EFI_D_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice->AriCapabilityOffset));
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EFI_D_INFO,
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"PCI ARI B%x.D%x.F%x - ARI Cap offset - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)PciIoDevice->AriCapabilityOffset
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));
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}
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}
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}
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}
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@ -2066,6 +2116,7 @@ CreatePciIoDevice (
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NULL
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NULL
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);
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);
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if (!EFI_ERROR (Status)) {
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if (!EFI_ERROR (Status)) {
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UINT32 SupportedPageSize;
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UINT16 VFStride;
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UINT16 VFStride;
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UINT16 FirstVFOffset;
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UINT16 FirstVFOffset;
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UINT16 Data16;
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UINT16 Data16;
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@ -2102,18 +2153,9 @@ CreatePciIoDevice (
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EfiPciIoWidthUint32,
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EfiPciIoWidthUint32,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,
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PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,
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1,
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1,
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&PciIoDevice->SystemPageSize
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&SupportedPageSize
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);
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);
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DEBUG ((
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PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & SupportedPageSize);
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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PciIoDevice->SystemPageSize
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));
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PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & PciIoDevice->SystemPageSize);
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ASSERT (PciIoDevice->SystemPageSize != 0);
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ASSERT (PciIoDevice->SystemPageSize != 0);
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PciIo->Pci.Write (
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PciIo->Pci.Write (
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@ -2123,14 +2165,6 @@ CreatePciIoDevice (
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1,
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1,
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&PciIoDevice->SystemPageSize
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&PciIoDevice->SystemPageSize
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);
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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PciIoDevice->SystemPageSize
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));
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//
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//
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// Adjust SystemPageSize for Alignment usage later
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// Adjust SystemPageSize for Alignment usage later
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//
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//
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@ -2150,15 +2184,6 @@ CreatePciIoDevice (
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1,
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1,
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&FirstVFOffset
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&FirstVFOffset
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);
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)FirstVFOffset
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));
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PciIo->Pci.Read (
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PciIo->Pci.Read (
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PciIo,
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PciIo,
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EfiPciIoWidthUint16,
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EfiPciIoWidthUint16,
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@ -2166,15 +2191,6 @@ CreatePciIoDevice (
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1,
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1,
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&PciIoDevice->InitialVFs
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&PciIoDevice->InitialVFs
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);
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)PciIoDevice->InitialVFs
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));
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PciIo->Pci.Read (
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PciIo->Pci.Read (
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PciIo,
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PciIo,
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EfiPciIoWidthUint16,
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EfiPciIoWidthUint16,
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@ -2182,15 +2198,6 @@ CreatePciIoDevice (
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1,
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1,
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&VFStride
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&VFStride
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);
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);
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DEBUG ((
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EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - VFStride - 0x%x\n",
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(UINTN)Bus,
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(UINTN)Device,
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(UINTN)Func,
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(UINTN)VFStride
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));
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//
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//
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// Calculate LastVF
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// Calculate LastVF
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//
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//
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@ -2201,22 +2208,16 @@ CreatePciIoDevice (
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// Calculate ReservedBusNum for this PF
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// Calculate ReservedBusNum for this PF
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//
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//
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PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
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PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
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DEBUG ((
|
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EFI_D_INFO,
|
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"PCI SR-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n",
|
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(UINTN)Bus,
|
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(UINTN)Device,
|
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(UINTN)Func,
|
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(UINTN)PciIoDevice->ReservedBusNum
|
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));
|
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|
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DEBUG ((
|
DEBUG ((
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EFI_D_INFO,
|
EFI_D_INFO,
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"PCI SR-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",
|
" SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
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(UINTN)Bus,
|
SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset
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(UINTN)Device,
|
));
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(UINTN)Func,
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DEBUG ((
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(UINTN)PciIoDevice->SrIovCapabilityOffset
|
EFI_D_INFO,
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|
" InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
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|
PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice->SrIovCapabilityOffset
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));
|
));
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}
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}
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}
|
}
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@ -2229,14 +2230,7 @@ CreatePciIoDevice (
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NULL
|
NULL
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);
|
);
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if (!EFI_ERROR (Status)) {
|
if (!EFI_ERROR (Status)) {
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DEBUG ((
|
DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
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EFI_D_INFO,
|
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"PCI MR-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",
|
|
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(UINTN)Bus,
|
|
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(UINTN)Device,
|
|
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(UINTN)Func,
|
|
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(UINTN)PciIoDevice->MrIovCapabilityOffset
|
|
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));
|
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}
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}
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}
|
}
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|
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@ -1,7 +1,7 @@
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/** @file
|
/** @file
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||||||
Internal library implementation for PCI Bus module.
|
Internal library implementation for PCI Bus module.
|
||||||
|
|
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Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||||
This program and the accompanying materials
|
This program and the accompanying materials
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
are licensed and made available under the terms and conditions of the BSD License
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
which accompanies this distribution. The full text of the license may be found at
|
||||||
@ -14,6 +14,19 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|||||||
|
|
||||||
#include "PciBus.h"
|
#include "PciBus.h"
|
||||||
|
|
||||||
|
GLOBAL_REMOVE_IF_UNREFERENCED
|
||||||
|
CHAR16 *mBarTypeStr[] = {
|
||||||
|
L"Unknow",
|
||||||
|
L" Io16",
|
||||||
|
L" Io32",
|
||||||
|
L" Mem32",
|
||||||
|
L"PMem32",
|
||||||
|
L" Mem64",
|
||||||
|
L"PMem64",
|
||||||
|
L" Io",
|
||||||
|
L" Mem",
|
||||||
|
L"Unknow"
|
||||||
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Retrieve the PCI Card device BAR information via PciIo interface.
|
Retrieve the PCI Card device BAR information via PciIo interface.
|
||||||
@ -153,6 +166,200 @@ RemoveRejectedPciDevices (
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Dump the resourc map of the bridge device.
|
||||||
|
|
||||||
|
@param[in] BridgeResource Resource descriptor of the bridge device.
|
||||||
|
**/
|
||||||
|
VOID
|
||||||
|
DumpBridgeResource (
|
||||||
|
IN PCI_RESOURCE_NODE *BridgeResource
|
||||||
|
)
|
||||||
|
{
|
||||||
|
LIST_ENTRY *Link;
|
||||||
|
PCI_RESOURCE_NODE *Resource;
|
||||||
|
PCI_BAR *Bar;
|
||||||
|
|
||||||
|
if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
|
||||||
|
DEBUG ((
|
||||||
|
EFI_D_INFO, "Type = %s; Base = 0x%x;\tLength = 0x%x;\tAlignment = 0x%x\n",
|
||||||
|
mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
|
||||||
|
BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
|
||||||
|
BridgeResource->Length, BridgeResource->Alignment
|
||||||
|
));
|
||||||
|
for ( Link = BridgeResource->ChildList.ForwardLink
|
||||||
|
; Link != &BridgeResource->ChildList
|
||||||
|
; Link = Link->ForwardLink
|
||||||
|
) {
|
||||||
|
Resource = RESOURCE_NODE_FROM_LINK (Link);
|
||||||
|
if (Resource->ResourceUsage == PciResUsageTypical) {
|
||||||
|
Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
|
||||||
|
DEBUG ((
|
||||||
|
EFI_D_INFO, " Base = 0x%x;\tLength = 0x%x;\tAlignment = 0x%x;\tOwner = %s ",
|
||||||
|
Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
|
||||||
|
IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :
|
||||||
|
IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :
|
||||||
|
L"PCI"
|
||||||
|
));
|
||||||
|
|
||||||
|
if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||
|
||||||
|
(IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||
|
||||||
|
(IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))
|
||||||
|
) {
|
||||||
|
//
|
||||||
|
// The resource requirement comes from the device itself.
|
||||||
|
//
|
||||||
|
DEBUG ((
|
||||||
|
EFI_D_INFO, " [%02x|%02x|%02x:%02x]\n",
|
||||||
|
Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
|
||||||
|
Resource->PciDev->FunctionNumber, Bar[Resource->Bar].Offset
|
||||||
|
));
|
||||||
|
} else {
|
||||||
|
//
|
||||||
|
// The resource requirement comes from the subordinate devices.
|
||||||
|
//
|
||||||
|
DEBUG ((
|
||||||
|
EFI_D_INFO, " [%02x|%02x|%02x:**]\n",
|
||||||
|
Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
|
||||||
|
Resource->PciDev->FunctionNumber
|
||||||
|
));
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
DEBUG ((EFI_D_INFO, " Padding:Length = 0x%x;\tAlignment = 0x%x\n", Resource->Length, Resource->Alignment));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Find the corresponding resource node for the Device in child list of BridgeResource.
|
||||||
|
|
||||||
|
@param[in] Device Pointer to PCI_IO_DEVICE.
|
||||||
|
@param[in] BridgeResource Pointer to PCI_RESOURCE_NODE.
|
||||||
|
|
||||||
|
@return !NULL The corresponding resource node for the Device.
|
||||||
|
@return NULL No corresponding resource node for the Device.
|
||||||
|
**/
|
||||||
|
PCI_RESOURCE_NODE *
|
||||||
|
FindResourceNode (
|
||||||
|
IN PCI_IO_DEVICE *Device,
|
||||||
|
IN PCI_RESOURCE_NODE *BridgeResource
|
||||||
|
)
|
||||||
|
{
|
||||||
|
LIST_ENTRY *Link;
|
||||||
|
PCI_RESOURCE_NODE *Resource;
|
||||||
|
|
||||||
|
for ( Link = BridgeResource->ChildList.ForwardLink
|
||||||
|
; Link != &BridgeResource->ChildList
|
||||||
|
; Link = Link->ForwardLink
|
||||||
|
) {
|
||||||
|
Resource = RESOURCE_NODE_FROM_LINK (Link);
|
||||||
|
if (Resource->PciDev == Device) {
|
||||||
|
return Resource;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Dump the resource map of all the devices under Bridge.
|
||||||
|
|
||||||
|
@param[in] Bridge Bridge device instance.
|
||||||
|
@param[in] IoNode IO resource descriptor for the bridge device.
|
||||||
|
@param[in] Mem32Node Mem32 resource descriptor for the bridge device.
|
||||||
|
@param[in] PMem32Node PMem32 resource descriptor for the bridge device.
|
||||||
|
@param[in] Mem64Node Mem64 resource descriptor for the bridge device.
|
||||||
|
@param[in] PMem64Node PMem64 resource descriptor for the bridge device.
|
||||||
|
**/
|
||||||
|
VOID
|
||||||
|
DumpResourceMap (
|
||||||
|
IN PCI_IO_DEVICE *Bridge,
|
||||||
|
IN PCI_RESOURCE_NODE *IoNode,
|
||||||
|
IN PCI_RESOURCE_NODE *Mem32Node,
|
||||||
|
IN PCI_RESOURCE_NODE *PMem32Node,
|
||||||
|
IN PCI_RESOURCE_NODE *Mem64Node,
|
||||||
|
IN PCI_RESOURCE_NODE *PMem64Node
|
||||||
|
)
|
||||||
|
{
|
||||||
|
EFI_STATUS Status;
|
||||||
|
LIST_ENTRY *Link;
|
||||||
|
PCI_IO_DEVICE *Device;
|
||||||
|
PCI_RESOURCE_NODE *ChildIoNode;
|
||||||
|
PCI_RESOURCE_NODE *ChildMem32Node;
|
||||||
|
PCI_RESOURCE_NODE *ChildPMem32Node;
|
||||||
|
PCI_RESOURCE_NODE *ChildMem64Node;
|
||||||
|
PCI_RESOURCE_NODE *ChildPMem64Node;
|
||||||
|
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *ToText;
|
||||||
|
CHAR16 *Str;
|
||||||
|
|
||||||
|
DEBUG ((EFI_D_INFO, "PciBus: Resource Map for "));
|
||||||
|
|
||||||
|
Status = gBS->OpenProtocol (
|
||||||
|
Bridge->Handle,
|
||||||
|
&gEfiPciRootBridgeIoProtocolGuid,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
EFI_OPEN_PROTOCOL_TEST_PROTOCOL
|
||||||
|
);
|
||||||
|
if (EFI_ERROR (Status)) {
|
||||||
|
DEBUG ((
|
||||||
|
EFI_D_INFO, "Bridge [%02x|%02x|%02x]\n",
|
||||||
|
Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber
|
||||||
|
));
|
||||||
|
} else {
|
||||||
|
Status = gBS->LocateProtocol (
|
||||||
|
&gEfiDevicePathToTextProtocolGuid,
|
||||||
|
NULL,
|
||||||
|
(VOID **) &ToText
|
||||||
|
);
|
||||||
|
Str = NULL;
|
||||||
|
if (!EFI_ERROR (Status)) {
|
||||||
|
Str = ToText->ConvertDevicePathToText (
|
||||||
|
DevicePathFromHandle (Bridge->Handle),
|
||||||
|
FALSE,
|
||||||
|
FALSE
|
||||||
|
);
|
||||||
|
}
|
||||||
|
DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
|
||||||
|
if (Str != NULL) {
|
||||||
|
FreePool (Str);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
DumpBridgeResource (IoNode);
|
||||||
|
DumpBridgeResource (Mem32Node);
|
||||||
|
DumpBridgeResource (PMem32Node);
|
||||||
|
DumpBridgeResource (Mem64Node);
|
||||||
|
DumpBridgeResource (PMem64Node);
|
||||||
|
DEBUG ((EFI_D_INFO, "\n"));
|
||||||
|
|
||||||
|
for ( Link = Bridge->ChildList.ForwardLink
|
||||||
|
; Link != &Bridge->ChildList
|
||||||
|
; Link = Link->ForwardLink
|
||||||
|
) {
|
||||||
|
Device = PCI_IO_DEVICE_FROM_LINK (Link);
|
||||||
|
if (IS_PCI_BRIDGE (&Device->Pci)) {
|
||||||
|
|
||||||
|
ChildIoNode = (IoNode == NULL ? NULL : FindResourceNode (Device, IoNode));
|
||||||
|
ChildMem32Node = (Mem32Node == NULL ? NULL : FindResourceNode (Device, Mem32Node));
|
||||||
|
ChildPMem32Node = (PMem32Node == NULL ? NULL : FindResourceNode (Device, PMem32Node));
|
||||||
|
ChildMem64Node = (Mem64Node == NULL ? NULL : FindResourceNode (Device, Mem64Node));
|
||||||
|
ChildPMem64Node = (PMem64Node == NULL ? NULL : FindResourceNode (Device, PMem64Node));
|
||||||
|
|
||||||
|
DumpResourceMap (
|
||||||
|
Device,
|
||||||
|
ChildIoNode,
|
||||||
|
ChildMem32Node,
|
||||||
|
ChildPMem32Node,
|
||||||
|
ChildMem64Node,
|
||||||
|
ChildPMem64Node
|
||||||
|
);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
|
Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
|
||||||
|
|
||||||
@ -244,7 +451,7 @@ PciHostBridgeResourceAllocator (
|
|||||||
RootBridgeDev,
|
RootBridgeDev,
|
||||||
0,
|
0,
|
||||||
FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,
|
FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,
|
||||||
0,
|
RB_IO_RANGE,
|
||||||
PciBarTypeIo16,
|
PciBarTypeIo16,
|
||||||
PciResUsageTypical
|
PciResUsageTypical
|
||||||
);
|
);
|
||||||
@ -253,7 +460,7 @@ PciHostBridgeResourceAllocator (
|
|||||||
RootBridgeDev,
|
RootBridgeDev,
|
||||||
0,
|
0,
|
||||||
0xFFFFF,
|
0xFFFFF,
|
||||||
0,
|
RB_MEM32_RANGE,
|
||||||
PciBarTypeMem32,
|
PciBarTypeMem32,
|
||||||
PciResUsageTypical
|
PciResUsageTypical
|
||||||
);
|
);
|
||||||
@ -262,7 +469,7 @@ PciHostBridgeResourceAllocator (
|
|||||||
RootBridgeDev,
|
RootBridgeDev,
|
||||||
0,
|
0,
|
||||||
0xFFFFF,
|
0xFFFFF,
|
||||||
0,
|
RB_PMEM32_RANGE,
|
||||||
PciBarTypePMem32,
|
PciBarTypePMem32,
|
||||||
PciResUsageTypical
|
PciResUsageTypical
|
||||||
);
|
);
|
||||||
@ -271,7 +478,7 @@ PciHostBridgeResourceAllocator (
|
|||||||
RootBridgeDev,
|
RootBridgeDev,
|
||||||
0,
|
0,
|
||||||
0xFFFFF,
|
0xFFFFF,
|
||||||
0,
|
RB_MEM64_RANGE,
|
||||||
PciBarTypeMem64,
|
PciBarTypeMem64,
|
||||||
PciResUsageTypical
|
PciResUsageTypical
|
||||||
);
|
);
|
||||||
@ -280,7 +487,7 @@ PciHostBridgeResourceAllocator (
|
|||||||
RootBridgeDev,
|
RootBridgeDev,
|
||||||
0,
|
0,
|
||||||
0xFFFFF,
|
0xFFFFF,
|
||||||
0,
|
RB_PMEM64_RANGE,
|
||||||
PciBarTypePMem64,
|
PciBarTypePMem64,
|
||||||
PciResUsageTypical
|
PciResUsageTypical
|
||||||
);
|
);
|
||||||
@ -597,19 +804,11 @@ PciHostBridgeResourceAllocator (
|
|||||||
// Create the entire system resource map from the information collected by
|
// Create the entire system resource map from the information collected by
|
||||||
// enumerator. Several resource tree was created
|
// enumerator. Several resource tree was created
|
||||||
//
|
//
|
||||||
GetResourceMap (
|
IoBridge = FindResourceNode (RootBridgeDev, &IoPool);
|
||||||
RootBridgeDev,
|
Mem32Bridge = FindResourceNode (RootBridgeDev, &Mem32Pool);
|
||||||
&IoBridge,
|
PMem32Bridge = FindResourceNode (RootBridgeDev, &PMem32Pool);
|
||||||
&Mem32Bridge,
|
Mem64Bridge = FindResourceNode (RootBridgeDev, &Mem64Pool);
|
||||||
&PMem32Bridge,
|
PMem64Bridge = FindResourceNode (RootBridgeDev, &PMem64Pool);
|
||||||
&Mem64Bridge,
|
|
||||||
&PMem64Bridge,
|
|
||||||
&IoPool,
|
|
||||||
&Mem32Pool,
|
|
||||||
&PMem32Pool,
|
|
||||||
&Mem64Pool,
|
|
||||||
&PMem64Pool
|
|
||||||
);
|
|
||||||
|
|
||||||
//
|
//
|
||||||
// Program IO resources
|
// Program IO resources
|
||||||
@ -651,6 +850,26 @@ PciHostBridgeResourceAllocator (
|
|||||||
PMem64Bridge
|
PMem64Bridge
|
||||||
);
|
);
|
||||||
|
|
||||||
|
IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;
|
||||||
|
Mem32Bridge ->PciDev->PciBar[Mem32Bridge ->Bar].BaseAddress = Mem32Base;
|
||||||
|
PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;
|
||||||
|
Mem64Bridge ->PciDev->PciBar[Mem64Bridge ->Bar].BaseAddress = Mem64Base;
|
||||||
|
PMem64Bridge->PciDev->PciBar[PMem64Bridge->Bar].BaseAddress = PMem64Base;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Dump the resource map for current root bridge
|
||||||
|
//
|
||||||
|
DEBUG_CODE (
|
||||||
|
DumpResourceMap (
|
||||||
|
RootBridgeDev,
|
||||||
|
IoBridge,
|
||||||
|
Mem32Bridge,
|
||||||
|
PMem32Bridge,
|
||||||
|
Mem64Bridge,
|
||||||
|
PMem64Bridge
|
||||||
|
);
|
||||||
|
);
|
||||||
|
|
||||||
FreePool (AcpiConfig);
|
FreePool (AcpiConfig);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -741,8 +960,6 @@ PciScanBus (
|
|||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
DEBUG((EFI_D_INFO, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));
|
|
||||||
|
|
||||||
//
|
//
|
||||||
// Get the PCI device information
|
// Get the PCI device information
|
||||||
//
|
//
|
||||||
@ -930,7 +1147,6 @@ PciScanBus (
|
|||||||
EfiPciBeforeChildBusEnumeration
|
EfiPciBeforeChildBusEnumeration
|
||||||
);
|
);
|
||||||
|
|
||||||
DEBUG((EFI_D_INFO, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber));
|
|
||||||
Status = PciScanBus (
|
Status = PciScanBus (
|
||||||
PciDevice,
|
PciDevice,
|
||||||
(UINT8) (SecondBus),
|
(UINT8) (SecondBus),
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
/** @file
|
/** @file
|
||||||
PCI resouces support functions implemntation for PCI Bus module.
|
PCI resouces support functions implemntation for PCI Bus module.
|
||||||
|
|
||||||
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||||
This program and the accompanying materials
|
This program and the accompanying materials
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
are licensed and made available under the terms and conditions of the BSD License
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
which accompanies this distribution. The full text of the license may be found at
|
||||||
@ -724,17 +724,6 @@ CreateVfResourceNode (
|
|||||||
{
|
{
|
||||||
PCI_RESOURCE_NODE *Node;
|
PCI_RESOURCE_NODE *Node;
|
||||||
|
|
||||||
DEBUG ((
|
|
||||||
EFI_D_INFO,
|
|
||||||
"PCI-IOV B%x.D%x.F%x - VfResource (Bar - 0x%x) (Type - 0x%x) (Length - 0x%x)\n",
|
|
||||||
(UINTN)PciDev->BusNumber,
|
|
||||||
(UINTN)PciDev->DeviceNumber,
|
|
||||||
(UINTN)PciDev->FunctionNumber,
|
|
||||||
(UINTN)Bar,
|
|
||||||
(UINTN)ResType,
|
|
||||||
(UINTN)Length
|
|
||||||
));
|
|
||||||
|
|
||||||
Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);
|
Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);
|
||||||
if (Node == NULL) {
|
if (Node == NULL) {
|
||||||
return Node;
|
return Node;
|
||||||
@ -1403,17 +1392,6 @@ ProgramVfBar (
|
|||||||
);
|
);
|
||||||
|
|
||||||
Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
|
Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
|
||||||
|
|
||||||
DEBUG ((
|
|
||||||
EFI_D_INFO,
|
|
||||||
"PCI-IOV B%x.D%x.F%x - VF Bar (Offset - 0x%x) 32Mem (Address - 0x%x)\n",
|
|
||||||
(UINTN)Node->PciDev->BusNumber,
|
|
||||||
(UINTN)Node->PciDev->DeviceNumber,
|
|
||||||
(UINTN)Node->PciDev->FunctionNumber,
|
|
||||||
(UINTN)(Node->PciDev->VfPciBar[Node->Bar]).Offset,
|
|
||||||
(UINTN)Address
|
|
||||||
));
|
|
||||||
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PciBarTypeMem64:
|
case PciBarTypeMem64:
|
||||||
@ -1440,17 +1418,6 @@ ProgramVfBar (
|
|||||||
);
|
);
|
||||||
|
|
||||||
Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
|
Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
|
||||||
|
|
||||||
DEBUG ((
|
|
||||||
EFI_D_INFO,
|
|
||||||
"PCI-IOV B%x.D%x.F%x - VF Bar (Offset - 0x%x) 64Mem (Address - 0x%lx)\n",
|
|
||||||
(UINTN)Node->PciDev->BusNumber,
|
|
||||||
(UINTN)Node->PciDev->DeviceNumber,
|
|
||||||
(UINTN)Node->PciDev->FunctionNumber,
|
|
||||||
(UINTN)(Node->PciDev->VfPciBar[Node->Bar]).Offset,
|
|
||||||
(UINT64)Address
|
|
||||||
));
|
|
||||||
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PciBarTypeIo16:
|
case PciBarTypeIo16:
|
||||||
@ -1727,123 +1694,6 @@ InitializeResourcePool (
|
|||||||
InitializeListHead (&ResourcePool->ChildList);
|
InitializeListHead (&ResourcePool->ChildList);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
Get all resource information for given Pci device.
|
|
||||||
|
|
||||||
@param PciDev Pci device instance.
|
|
||||||
@param IoBridge Io resource node.
|
|
||||||
@param Mem32Bridge 32-bit memory node.
|
|
||||||
@param PMem32Bridge 32-bit Pmemory node.
|
|
||||||
@param Mem64Bridge 64-bit memory node.
|
|
||||||
@param PMem64Bridge 64-bit PMemory node.
|
|
||||||
@param IoPool Link list header for Io resource.
|
|
||||||
@param Mem32Pool Link list header for 32-bit memory.
|
|
||||||
@param PMem32Pool Link list header for 32-bit Prefetchable memory.
|
|
||||||
@param Mem64Pool Link list header for 64-bit memory.
|
|
||||||
@param PMem64Pool Link list header for 64-bit Prefetchable memory.
|
|
||||||
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
GetResourceMap (
|
|
||||||
IN PCI_IO_DEVICE *PciDev,
|
|
||||||
IN PCI_RESOURCE_NODE **IoBridge,
|
|
||||||
IN PCI_RESOURCE_NODE **Mem32Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE **PMem32Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE **Mem64Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE **PMem64Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE *IoPool,
|
|
||||||
IN PCI_RESOURCE_NODE *Mem32Pool,
|
|
||||||
IN PCI_RESOURCE_NODE *PMem32Pool,
|
|
||||||
IN PCI_RESOURCE_NODE *Mem64Pool,
|
|
||||||
IN PCI_RESOURCE_NODE *PMem64Pool
|
|
||||||
)
|
|
||||||
{
|
|
||||||
|
|
||||||
PCI_RESOURCE_NODE *Temp;
|
|
||||||
LIST_ENTRY *CurrentLink;
|
|
||||||
|
|
||||||
CurrentLink = IoPool->ChildList.ForwardLink;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Get Io resource map
|
|
||||||
//
|
|
||||||
while (CurrentLink != &IoPool->ChildList) {
|
|
||||||
|
|
||||||
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
|
|
||||||
|
|
||||||
if (Temp->PciDev == PciDev) {
|
|
||||||
*IoBridge = Temp;
|
|
||||||
}
|
|
||||||
|
|
||||||
CurrentLink = CurrentLink->ForwardLink;
|
|
||||||
}
|
|
||||||
|
|
||||||
//
|
|
||||||
// Get Mem32 resource map
|
|
||||||
//
|
|
||||||
CurrentLink = Mem32Pool->ChildList.ForwardLink;
|
|
||||||
|
|
||||||
while (CurrentLink != &Mem32Pool->ChildList) {
|
|
||||||
|
|
||||||
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
|
|
||||||
|
|
||||||
if (Temp->PciDev == PciDev) {
|
|
||||||
*Mem32Bridge = Temp;
|
|
||||||
}
|
|
||||||
|
|
||||||
CurrentLink = CurrentLink->ForwardLink;
|
|
||||||
}
|
|
||||||
|
|
||||||
//
|
|
||||||
// Get Pmem32 resource map
|
|
||||||
//
|
|
||||||
CurrentLink = PMem32Pool->ChildList.ForwardLink;
|
|
||||||
|
|
||||||
while (CurrentLink != &PMem32Pool->ChildList) {
|
|
||||||
|
|
||||||
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
|
|
||||||
|
|
||||||
if (Temp->PciDev == PciDev) {
|
|
||||||
*PMem32Bridge = Temp;
|
|
||||||
}
|
|
||||||
|
|
||||||
CurrentLink = CurrentLink->ForwardLink;
|
|
||||||
}
|
|
||||||
|
|
||||||
//
|
|
||||||
// Get Mem64 resource map
|
|
||||||
//
|
|
||||||
CurrentLink = Mem64Pool->ChildList.ForwardLink;
|
|
||||||
|
|
||||||
while (CurrentLink != &Mem64Pool->ChildList) {
|
|
||||||
|
|
||||||
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
|
|
||||||
|
|
||||||
if (Temp->PciDev == PciDev) {
|
|
||||||
*Mem64Bridge = Temp;
|
|
||||||
}
|
|
||||||
|
|
||||||
CurrentLink = CurrentLink->ForwardLink;
|
|
||||||
}
|
|
||||||
|
|
||||||
//
|
|
||||||
// Get Pmem64 resource map
|
|
||||||
//
|
|
||||||
CurrentLink = PMem64Pool->ChildList.ForwardLink;
|
|
||||||
|
|
||||||
while (CurrentLink != &PMem64Pool->ChildList) {
|
|
||||||
|
|
||||||
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
|
|
||||||
|
|
||||||
if (Temp->PciDev == PciDev) {
|
|
||||||
*PMem64Bridge = Temp;
|
|
||||||
}
|
|
||||||
|
|
||||||
CurrentLink = CurrentLink->ForwardLink;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Destory given resource tree.
|
Destory given resource tree.
|
||||||
|
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
/** @file
|
/** @file
|
||||||
PCI resouces support functions declaration for PCI Bus module.
|
PCI resouces support functions declaration for PCI Bus module.
|
||||||
|
|
||||||
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||||
This program and the accompanying materials
|
This program and the accompanying materials
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
are licensed and made available under the terms and conditions of the BSD License
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
which accompanies this distribution. The full text of the license may be found at
|
||||||
@ -16,9 +16,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|||||||
#define _EFI_PCI_RESOURCE_SUPPORT_H_
|
#define _EFI_PCI_RESOURCE_SUPPORT_H_
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
PciResUsageTypical = 0,
|
PciResUsageTypical,
|
||||||
PciResUsagePadding,
|
PciResUsagePadding
|
||||||
PciResUsageOptionRomProcessing
|
|
||||||
} PCI_RESOURCE_USAGE;
|
} PCI_RESOURCE_USAGE;
|
||||||
|
|
||||||
#define PCI_RESOURCE_SIGNATURE SIGNATURE_32 ('p', 'c', 'r', 'c')
|
#define PCI_RESOURCE_SIGNATURE SIGNATURE_32 ('p', 'c', 'r', 'c')
|
||||||
@ -382,37 +381,6 @@ InitializeResourcePool (
|
|||||||
IN PCI_BAR_TYPE ResourceType
|
IN PCI_BAR_TYPE ResourceType
|
||||||
);
|
);
|
||||||
|
|
||||||
/**
|
|
||||||
Get all resource information for given Pci device.
|
|
||||||
|
|
||||||
@param PciDev Pci device instance.
|
|
||||||
@param IoBridge Io resource node.
|
|
||||||
@param Mem32Bridge 32-bit memory node.
|
|
||||||
@param PMem32Bridge 32-bit Pmemory node.
|
|
||||||
@param Mem64Bridge 64-bit memory node.
|
|
||||||
@param PMem64Bridge 64-bit PMemory node.
|
|
||||||
@param IoPool Link list header for Io resource.
|
|
||||||
@param Mem32Pool Link list header for 32-bit memory.
|
|
||||||
@param PMem32Pool Link list header for 32-bit Prefetchable memory.
|
|
||||||
@param Mem64Pool Link list header for 64-bit memory.
|
|
||||||
@param PMem64Pool Link list header for 64-bit Prefetchable memory.
|
|
||||||
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
GetResourceMap (
|
|
||||||
IN PCI_IO_DEVICE *PciDev,
|
|
||||||
IN PCI_RESOURCE_NODE **IoBridge,
|
|
||||||
IN PCI_RESOURCE_NODE **Mem32Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE **PMem32Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE **Mem64Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE **PMem64Bridge,
|
|
||||||
IN PCI_RESOURCE_NODE *IoPool,
|
|
||||||
IN PCI_RESOURCE_NODE *Mem32Pool,
|
|
||||||
IN PCI_RESOURCE_NODE *PMem32Pool,
|
|
||||||
IN PCI_RESOURCE_NODE *Mem64Pool,
|
|
||||||
IN PCI_RESOURCE_NODE *PMem64Pool
|
|
||||||
);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Destory given resource tree.
|
Destory given resource tree.
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user