Always set WP in CR0.

Always set RW+P bit for page table by default.

So that we can use write-protection for code later.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524

UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S

@@ -123,7 +123,7 @@ L11:
 L12:                                       # as cr4.PGE is not set here, refresh cr3
     movl    %eax, %cr4                     # in PreModifyMtrrs() to flush TLB.
     movl    %cr0, %ebx
-    orl     $0x080000000, %ebx             # enable paging
+    orl     $0x080010000, %ebx             # enable paging + WP
     movl    %ebx, %cr0
     leal    DSC_OFFSET(%edi),%ebx
     movw    DSC_DS(%ebx),%ax