sravan/system76-edk2
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Always set WP in CR0.

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Always set RW+P bit for page table by default.

So that we can use write-protection for code later.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Yao, Jiewen
2015-11-26 07:01:08 +00:00
committed by jyao1
parent 989edf1633
commit 8e496a7abc
9 changed files with 28 additions and 24 deletions
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2
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
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@@ -129,7 +129,7 @@ gSmiCr3 DD ?
@@: ; as cr4.PGE is not set here, refresh cr3
mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
mov ebx, cr0
or ebx, 080000000h ; enable paging
or ebx, 080010000h ; enable paging + WP
mov cr0, ebx
lea ebx, [edi + DSC_OFFSET]
mov ax, [ebx + DSC_DS]