Always set WP in CR0.

Always set RW+P bit for page table by default.

So that we can use write-protection for code later.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524

UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm

@@ -140,7 +140,7 @@ Base:
     or      ah, 1
     wrmsr
     mov     rbx, cr0
-    bts     ebx, 31
+    or      ebx, 080010000h            ; enable paging + WP
     mov     cr0, rbx
     retf
 @LongMode:                              ; long mode (64-bit code) starts here