Import two CPU Exception Handler Library instances: SecPeiCpuExceptionHandler.inf and DxeSmmCpuExceptionHandler.inf.
Signed-off-by: vanjeff Reviewed-by: jyao1 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13098 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
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/** @file
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x64 CPU Exception Hanlder.
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Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CpuExceptionCommon.h"
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/**
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Internal function to setup CPU exception handlers.
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**/
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VOID
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InternalSetupCpuExceptionHandlers (
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VOID
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)
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{
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IA32_DESCRIPTOR IdtDescriptor;
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UINTN IdtSize;
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EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
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UINT16 CodeSegment;
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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UINTN Index;
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UINTN InterruptHandler;
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//
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// Read IDT descriptor and calculate IDT size
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//
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AsmReadIdtr (&IdtDescriptor);
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IdtSize = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
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if (IdtSize > CPU_EXCEPTION_NUM) {
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//
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// CPU exeption library only setup CPU_EXCEPTION_NUM exception handler at most
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//
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IdtSize = CPU_EXCEPTION_NUM;
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}
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//
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// Use current CS as the segment selector of interrupt gate in IDT
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//
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CodeSegment = AsmReadCs ();
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
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GetTemplateAddressMap (&TemplateMap);
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for (Index = 0; Index < IdtSize; Index ++) {
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InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
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IdtEntry[Index].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
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IdtEntry[Index].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
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IdtEntry[Index].Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
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IdtEntry[Index].Bits.Selector = CodeSegment;
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IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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}
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}
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/**
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Common exception handler.
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@param ExceptionType Exception type.
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@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
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**/
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VOID
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DumpCpuContent (
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IN UINTN ExceptionType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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UINTN ImageBase;
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UINTN EntryPoint;
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InternalPrintMessage (
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"!!!! X64 Exception Type - %016lx CPU Apic ID - %08x !!!!\n",
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ExceptionType,
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GetApicId ()
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);
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InternalPrintMessage (
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"RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n",
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SystemContext.SystemContextX64->Rip,
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SystemContext.SystemContextX64->Cs,
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SystemContext.SystemContextX64->Rflags
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);
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if (mErrorCodeFlag & (1 << ExceptionType)) {
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InternalPrintMessage (
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"ExceptionData - %016lx\n",
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SystemContext.SystemContextX64->ExceptionData
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);
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}
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InternalPrintMessage (
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"RAX - %016lx, RCX - %016lx, RDX - %016lx\n",
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SystemContext.SystemContextX64->Rax,
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SystemContext.SystemContextX64->Rcx,
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SystemContext.SystemContextX64->Rdx
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);
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InternalPrintMessage (
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"RBX - %016lx, RSP - %016lx, RBP - %016lx\n",
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SystemContext.SystemContextX64->Rbx,
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SystemContext.SystemContextX64->Rsp,
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SystemContext.SystemContextX64->Rbp
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);
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InternalPrintMessage (
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"RSI - %016lx, RDI - %016lx\n",
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SystemContext.SystemContextX64->Rsi,
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SystemContext.SystemContextX64->Rdi
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);
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InternalPrintMessage (
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"R8 - %016lx, R9 - %016lx, R10 - %016lx\n",
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SystemContext.SystemContextX64->R8,
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SystemContext.SystemContextX64->R9,
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SystemContext.SystemContextX64->R10
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);
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InternalPrintMessage (
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"R11 - %016lx, R12 - %016lx, R13 - %016lx\n",
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SystemContext.SystemContextX64->R11,
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SystemContext.SystemContextX64->R12,
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SystemContext.SystemContextX64->R13
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);
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InternalPrintMessage (
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"R14 - %016lx, R15 - %016lx\n",
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SystemContext.SystemContextX64->R14,
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SystemContext.SystemContextX64->R15
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);
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InternalPrintMessage (
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"DS - %016lx, ES - %016lx, FS - %016lx\n",
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SystemContext.SystemContextX64->Ds,
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SystemContext.SystemContextX64->Es,
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SystemContext.SystemContextX64->Fs
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);
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InternalPrintMessage (
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"GS - %016lx, SS - %016lx\n",
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SystemContext.SystemContextX64->Gs,
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SystemContext.SystemContextX64->Ss
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);
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InternalPrintMessage (
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"CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",
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SystemContext.SystemContextX64->Cr0,
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SystemContext.SystemContextX64->Cr2,
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SystemContext.SystemContextX64->Cr3
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);
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InternalPrintMessage (
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"CR4 - %016lx, CR8 - %016lx\n",
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SystemContext.SystemContextX64->Cr4,
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SystemContext.SystemContextX64->Cr8
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);
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InternalPrintMessage (
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"DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",
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SystemContext.SystemContextX64->Dr0,
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SystemContext.SystemContextX64->Dr1,
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SystemContext.SystemContextX64->Dr2
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);
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InternalPrintMessage (
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"DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",
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SystemContext.SystemContextX64->Dr3,
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SystemContext.SystemContextX64->Dr6,
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SystemContext.SystemContextX64->Dr7
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);
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InternalPrintMessage (
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"GDTR - %016lx %016lx, LDTR - %016lx\n",
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SystemContext.SystemContextX64->Gdtr[0],
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SystemContext.SystemContextX64->Gdtr[1],
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SystemContext.SystemContextX64->Ldtr
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);
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InternalPrintMessage (
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"IDTR - %016lx %016lx, TR - %016lx\n",
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SystemContext.SystemContextX64->Idtr[0],
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SystemContext.SystemContextX64->Idtr[1],
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SystemContext.SystemContextX64->Tr
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);
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InternalPrintMessage (
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"FXSAVE_STATE - %016lx\n",
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&SystemContext.SystemContextX64->FxSaveState
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);
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//
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// Find module image base and module entry point by RIP
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//
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ImageBase = FindModuleImageBase (SystemContext.SystemContextX64->Rip, &EntryPoint);
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if (ImageBase != 0) {
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InternalPrintMessage (
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" (ImageBase=%016lx, EntryPoint=%016lx) !!!!\n",
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ImageBase,
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EntryPoint
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);
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}
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}
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@@ -0,0 +1,406 @@
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#------------------------------------------------------------------------------ ;
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# Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# ExceptionHandlerAsm.S
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#
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# Abstract:
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#
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# x64 CPU Exception Handler
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#
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# Notes:
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#
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#------------------------------------------------------------------------------
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#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
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ASM_GLOBAL ASM_PFX(CommonExceptionHandler)
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ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
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.text
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#
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# point to the external interrupt vector table
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#
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Exception0Handle:
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pushq $0
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jmp ASM_PFX(CommonInterruptEntry)
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Exception1Handle:
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pushq $1
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jmp ASM_PFX(CommonInterruptEntry)
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Exception2Handle:
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pushq $2
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jmp ASM_PFX(CommonInterruptEntry)
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Exception3Handle:
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pushq $3
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jmp ASM_PFX(CommonInterruptEntry)
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Exception4Handle:
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pushq $4
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jmp ASM_PFX(CommonInterruptEntry)
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Exception5Handle:
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pushq $5
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jmp ASM_PFX(CommonInterruptEntry)
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Exception6Handle:
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pushq $6
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jmp ASM_PFX(CommonInterruptEntry)
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Exception7Handle:
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pushq $7
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jmp ASM_PFX(CommonInterruptEntry)
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Exception8Handle:
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pushq $8
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jmp ASM_PFX(CommonInterruptEntry)
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Exception9Handle:
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pushq $9
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jmp ASM_PFX(CommonInterruptEntry)
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Exception10Handle:
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pushq $10
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jmp ASM_PFX(CommonInterruptEntry)
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Exception11Handle:
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pushq $11
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jmp ASM_PFX(CommonInterruptEntry)
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Exception12Handle:
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pushq $12
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jmp ASM_PFX(CommonInterruptEntry)
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Exception13Handle:
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pushq $13
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jmp ASM_PFX(CommonInterruptEntry)
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Exception14Handle:
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pushq $14
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jmp ASM_PFX(CommonInterruptEntry)
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Exception15Handle:
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pushq $15
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jmp ASM_PFX(CommonInterruptEntry)
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Exception16Handle:
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pushq $16
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jmp ASM_PFX(CommonInterruptEntry)
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Exception17Handle:
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pushq $17
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jmp ASM_PFX(CommonInterruptEntry)
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Exception18Handle:
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pushq $18
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jmp ASM_PFX(CommonInterruptEntry)
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Exception19Handle:
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pushq $19
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jmp ASM_PFX(CommonInterruptEntry)
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Exception20Handle:
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pushq $20
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jmp ASM_PFX(CommonInterruptEntry)
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Exception21Handle:
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pushq $21
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jmp ASM_PFX(CommonInterruptEntry)
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Exception22Handle:
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pushq $22
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jmp ASM_PFX(CommonInterruptEntry)
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Exception23Handle:
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pushq $23
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jmp ASM_PFX(CommonInterruptEntry)
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Exception24Handle:
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pushq $24
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jmp ASM_PFX(CommonInterruptEntry)
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Exception25Handle:
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pushq $25
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jmp ASM_PFX(CommonInterruptEntry)
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Exception26Handle:
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pushq $26
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jmp ASM_PFX(CommonInterruptEntry)
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Exception27Handle:
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pushq $27
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jmp ASM_PFX(CommonInterruptEntry)
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Exception28Handle:
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pushq $28
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jmp ASM_PFX(CommonInterruptEntry)
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Exception29Handle:
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pushq $29
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jmp ASM_PFX(CommonInterruptEntry)
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Exception30Handle:
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pushq $30
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jmp ASM_PFX(CommonInterruptEntry)
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Exception31Handle:
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pushq $31
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jmp ASM_PFX(CommonInterruptEntry)
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#---------------------------------------;
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# CommonInterruptEntry ;
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#---------------------------------------;
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# The follow algorithm is used for the common interrupt routine.
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ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
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ASM_PFX(CommonInterruptEntry):
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cli
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#
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# All interrupt handlers are invoked through interrupt gates, so
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# IF flag automatically cleared at the entry point
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#
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#
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# Calculate vector number
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#
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xchgq (%rsp), %rcx # get the return address of call, actually, it is the address of vector number.
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cmp $32, %ecx # Intel reserved vector for exceptions?
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jae NoErrorCode
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pushq %rax
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leaq ASM_PFX(mErrorCodeFlag)(%rip), %rax
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bt %ecx, (%rax)
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popq %rax
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jc CommonInterruptEntry_al_0000
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NoErrorCode:
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#
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# Push a dummy error code on the stack
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# to maintain coherent stack map
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#
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pushq (%rsp)
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movq $0, 8(%rsp)
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CommonInterruptEntry_al_0000:
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pushq %rbp
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movq %rsp, %rbp
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#
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# Stack:
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# +---------------------+ <-- 16-byte aligned ensured by processor
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# + Old SS +
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# +---------------------+
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# + Old RSP +
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# +---------------------+
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# + RFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + RIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + RCX / Vector Number +
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# +---------------------+
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# + RBP +
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# +---------------------+ <-- RBP, 16-byte aligned
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#
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#
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# Since here the stack pointer is 16-byte aligned, so
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# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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# is 16-byte aligned
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#
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#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %r9
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pushq %r8
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pushq %rax
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pushq 8(%rbp) # RCX
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pushq %rdx
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pushq %rbx
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pushq 48(%rbp) # RSP
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pushq (%rbp) # RBP
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pushq %rsi
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pushq %rdi
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#; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzwq 56(%rbp), %rax
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pushq %rax # for ss
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movzwq 32(%rbp), %rax
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pushq %rax # for cs
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movl %ds, %eax
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pushq %rax
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movl %es, %eax
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pushq %rax
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movl %fs, %eax
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pushq %rax
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movl %gs, %eax
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pushq %rax
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movq %rcx, 8(%rbp) # save vector number
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#; UINT64 Rip;
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pushq 24(%rbp)
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#; UINT64 Gdtr[2], Idtr[2];
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xorq %rax, %rax
|
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pushq %rax
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pushq %rax
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sidt (%rsp)
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xchgq 2(%rsp), %rax
|
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xchgq (%rsp), %rax
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xchgq 8(%rsp), %rax
|
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|
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xorq %rax, %rax
|
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pushq %rax
|
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pushq %rax
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sgdt (%rsp)
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xchgq 2(%rsp), %rax
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xchgq (%rsp), %rax
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xchgq 8(%rsp), %rax
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|
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#; UINT64 Ldtr, Tr;
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xorq %rax, %rax
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str %ax
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pushq %rax
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sldt %ax
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pushq %rax
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|
||||
#; UINT64 RFlags;
|
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pushq 40(%rbp)
|
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|
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#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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movq %cr8, %rax
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pushq %rax
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||||
movq %cr4, %rax
|
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orq $0x208, %rax
|
||||
movq %rax, %cr4
|
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pushq %rax
|
||||
mov %cr3, %rax
|
||||
pushq %rax
|
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mov %cr2, %rax
|
||||
pushq %rax
|
||||
xorq %rax, %rax
|
||||
pushq %rax
|
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mov %cr0, %rax
|
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pushq %rax
|
||||
|
||||
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
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movq %dr7, %rax
|
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pushq %rax
|
||||
movq %dr6, %rax
|
||||
pushq %rax
|
||||
movq %dr3, %rax
|
||||
pushq %rax
|
||||
movq %dr2, %rax
|
||||
pushq %rax
|
||||
movq %dr1, %rax
|
||||
pushq %rax
|
||||
movq %dr0, %rax
|
||||
pushq %rax
|
||||
|
||||
#; FX_SAVE_STATE_X64 FxSaveState;
|
||||
subq $512, %rsp
|
||||
movq %rsp, %rdi
|
||||
.byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
|
||||
|
||||
#; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
|
||||
cld
|
||||
|
||||
#; UINT32 ExceptionData;
|
||||
pushq 16(%rbp)
|
||||
|
||||
#; Prepare parameter and call
|
||||
mov 8(%rbp), %rcx
|
||||
mov %rsp, %rdx
|
||||
#
|
||||
# Per X64 calling convention, allocate maximum parameter stack space
|
||||
# and make sure RSP is 16-byte aligned
|
||||
#
|
||||
subq $40, %rsp
|
||||
call ASM_PFX(CommonExceptionHandler)
|
||||
addq $40, %rsp
|
||||
|
||||
cli
|
||||
#; UINT64 ExceptionData;
|
||||
addq $8, %rsp
|
||||
|
||||
#; FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
movq %rsp, %rsi
|
||||
.byte 0x0f, 0x0ae, 0x0E # fxrstor [rsi]
|
||||
addq $512, %rsp
|
||||
|
||||
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
#; Skip restoration of DRx registers to support in-circuit emualators
|
||||
#; or debuggers set breakpoint in interrupt/exception context
|
||||
addq $48, %rsp
|
||||
|
||||
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
popq %rax
|
||||
movq %rax, %cr0
|
||||
addq $8, %rsp # not for Cr1
|
||||
popq %rax
|
||||
movq %rax, %cr2
|
||||
popq %rax
|
||||
movq %rax, %cr3
|
||||
popq %rax
|
||||
movq %rax, %cr4
|
||||
popq %rax
|
||||
movq %rax, %cr8
|
||||
|
||||
#; UINT64 RFlags;
|
||||
popq 40(%rbp)
|
||||
|
||||
#; UINT64 Ldtr, Tr;
|
||||
#; UINT64 Gdtr[2], Idtr[2];
|
||||
#; Best not let anyone mess with these particular registers...
|
||||
addq $48, %rsp
|
||||
|
||||
#; UINT64 Rip;
|
||||
popq 24(%rbp)
|
||||
|
||||
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
popq %rax
|
||||
# mov %rax, %gs ; not for gs
|
||||
popq %rax
|
||||
# mov %rax, %fs ; not for fs
|
||||
# (X64 will not use fs and gs, so we do not restore it)
|
||||
popq %rax
|
||||
movl %eax, %es
|
||||
popq %rax
|
||||
movl %eax, %ds
|
||||
popq 32(%rbp) # for cs
|
||||
popq 56(%rbp) # for ss
|
||||
|
||||
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
popq %rdi
|
||||
popq %rsi
|
||||
addq $8, %rsp # not for rbp
|
||||
popq 48(%rbp) # for rsp
|
||||
popq %rbx
|
||||
popq %rdx
|
||||
popq %rcx
|
||||
popq %rax
|
||||
popq %r8
|
||||
popq %r9
|
||||
popq %r10
|
||||
popq %r11
|
||||
popq %r12
|
||||
popq %r13
|
||||
popq %r14
|
||||
popq %r15
|
||||
|
||||
movq %rbp, %rsp
|
||||
popq %rbp
|
||||
addq $16, %rsp
|
||||
iretq
|
||||
|
||||
|
||||
#-------------------------------------------------------------------------------------
|
||||
# AsmGetAddressMap (&AddressMap);
|
||||
#-------------------------------------------------------------------------------------
|
||||
# comments here for definition of address map
|
||||
ASM_GLOBAL ASM_PFX(GetTemplateAddressMap)
|
||||
ASM_PFX(GetTemplateAddressMap):
|
||||
|
||||
movabsq $Exception0Handle, %rax
|
||||
movq %rax, (%rcx)
|
||||
movq $(Exception1Handle - Exception0Handle), 0x08(%rcx)
|
||||
|
||||
ret
|
||||
|
||||
#END
|
||||
|
||||
|
||||
@@ -0,0 +1,407 @@
|
||||
;------------------------------------------------------------------------------ ;
|
||||
; Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
|
||||
; This program and the accompanying materials
|
||||
; are licensed and made available under the terms and conditions of the BSD License
|
||||
; which accompanies this distribution. The full text of the license may be found at
|
||||
; http://opensource.org/licenses/bsd-license.php.
|
||||
;
|
||||
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
;
|
||||
; Module Name:
|
||||
;
|
||||
; ExceptionHandlerAsm.Asm
|
||||
;
|
||||
; Abstract:
|
||||
;
|
||||
; x64 CPU Exception Handler
|
||||
;
|
||||
; Notes:
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
;
|
||||
; CommonExceptionHandler()
|
||||
;
|
||||
CommonExceptionHandler PROTO C
|
||||
|
||||
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
|
||||
|
||||
data SEGMENT
|
||||
|
||||
CommonEntryAddr dq CommonInterruptEntry;
|
||||
|
||||
.code
|
||||
|
||||
Exception0Handle:
|
||||
push 0
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception1Handle:
|
||||
push 1
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception2Handle:
|
||||
push 2
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception3Handle:
|
||||
push 3
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception4Handle:
|
||||
push 4
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception5Handle:
|
||||
push 5
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception6Handle:
|
||||
push 6
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception7Handle:
|
||||
push 7
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception8Handle:
|
||||
push 8
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception9Handle:
|
||||
push 9
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception10Handle:
|
||||
push 10
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception11Handle:
|
||||
push 11
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception12Handle:
|
||||
push 12
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception13Handle:
|
||||
push 13
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception14Handle:
|
||||
push 14
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception15Handle:
|
||||
push 15
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception16Handle:
|
||||
push 16
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception17Handle:
|
||||
push 17
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception18Handle:
|
||||
push 18
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception19Handle:
|
||||
push 19
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception20Handle:
|
||||
push 20
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception21Handle:
|
||||
push 21
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception22Handle:
|
||||
push 22
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception23Handle:
|
||||
push 23
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception24Handle:
|
||||
push 24
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception25Handle:
|
||||
push 25
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception26Handle:
|
||||
push 26
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception27Handle:
|
||||
push 27
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception28Handle:
|
||||
push 28
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception29Handle:
|
||||
push 29
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception30Handle:
|
||||
push 30
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
Exception31Handle:
|
||||
push 31
|
||||
jmp qword ptr [CommonEntryAddr]
|
||||
|
||||
;CommonInterruptEntrypoint:
|
||||
;---------------------------------------;
|
||||
; _CommonEntry ;
|
||||
;----------------------------------------------------------------------------;
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
; Entry from each interrupt with a push eax and eax=interrupt number
|
||||
|
||||
;---------------------------------------;
|
||||
; CommonInterruptEntry ;
|
||||
;---------------------------------------;
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
|
||||
CommonInterruptEntry PROC PUBLIC
|
||||
cli
|
||||
;
|
||||
; All interrupt handlers are invoked through interrupt gates, so
|
||||
; IF flag automatically cleared at the entry point
|
||||
;
|
||||
;
|
||||
; Calculate vector number
|
||||
;
|
||||
xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.
|
||||
cmp ecx, 32 ; Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
bt mErrorCodeFlag, ecx
|
||||
jc @F
|
||||
|
||||
NoErrorCode:
|
||||
|
||||
;
|
||||
; Push a dummy error code on the stack
|
||||
; to maintain coherent stack map
|
||||
;
|
||||
push [rsp]
|
||||
mov qword ptr [rsp + 8], 0
|
||||
@@:
|
||||
push rbp
|
||||
mov rbp, rsp
|
||||
|
||||
;
|
||||
; Stack:
|
||||
; +---------------------+ <-- 16-byte aligned ensured by processor
|
||||
; + Old SS +
|
||||
; +---------------------+
|
||||
; + Old RSP +
|
||||
; +---------------------+
|
||||
; + RFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + RIP +
|
||||
; +---------------------+
|
||||
; + Error Code +
|
||||
; +---------------------+
|
||||
; + RCX / Vector Number +
|
||||
; +---------------------+
|
||||
; + RBP +
|
||||
; +---------------------+ <-- RBP, 16-byte aligned
|
||||
;
|
||||
|
||||
|
||||
;
|
||||
; Since here the stack pointer is 16-byte aligned, so
|
||||
; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
|
||||
; is 16-byte aligned
|
||||
;
|
||||
|
||||
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
push r15
|
||||
push r14
|
||||
push r13
|
||||
push r12
|
||||
push r11
|
||||
push r10
|
||||
push r9
|
||||
push r8
|
||||
push rax
|
||||
push qword ptr [rbp + 8] ; RCX
|
||||
push rdx
|
||||
push rbx
|
||||
push qword ptr [rbp + 48] ; RSP
|
||||
push qword ptr [rbp] ; RBP
|
||||
push rsi
|
||||
push rdi
|
||||
|
||||
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
|
||||
movzx rax, word ptr [rbp + 56]
|
||||
push rax ; for ss
|
||||
movzx rax, word ptr [rbp + 32]
|
||||
push rax ; for cs
|
||||
mov rax, ds
|
||||
push rax
|
||||
mov rax, es
|
||||
push rax
|
||||
mov rax, fs
|
||||
push rax
|
||||
mov rax, gs
|
||||
push rax
|
||||
|
||||
mov [rbp + 8], rcx ; save vector number
|
||||
|
||||
;; UINT64 Rip;
|
||||
push qword ptr [rbp + 24]
|
||||
|
||||
;; UINT64 Gdtr[2], Idtr[2];
|
||||
xor rax, rax
|
||||
push rax
|
||||
push rax
|
||||
sidt [rsp]
|
||||
xchg rax, [rsp + 2]
|
||||
xchg rax, [rsp]
|
||||
xchg rax, [rsp + 8]
|
||||
|
||||
xor rax, rax
|
||||
push rax
|
||||
push rax
|
||||
sgdt [rsp]
|
||||
xchg rax, [rsp + 2]
|
||||
xchg rax, [rsp]
|
||||
xchg rax, [rsp + 8]
|
||||
|
||||
;; UINT64 Ldtr, Tr;
|
||||
xor rax, rax
|
||||
str ax
|
||||
push rax
|
||||
sldt ax
|
||||
push rax
|
||||
|
||||
;; UINT64 RFlags;
|
||||
push qword ptr [rbp + 40]
|
||||
|
||||
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
mov rax, cr8
|
||||
push rax
|
||||
mov rax, cr4
|
||||
or rax, 208h
|
||||
mov cr4, rax
|
||||
push rax
|
||||
mov rax, cr3
|
||||
push rax
|
||||
mov rax, cr2
|
||||
push rax
|
||||
xor rax, rax
|
||||
push rax
|
||||
mov rax, cr0
|
||||
push rax
|
||||
|
||||
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
mov rax, dr7
|
||||
push rax
|
||||
mov rax, dr6
|
||||
push rax
|
||||
mov rax, dr3
|
||||
push rax
|
||||
mov rax, dr2
|
||||
push rax
|
||||
mov rax, dr1
|
||||
push rax
|
||||
mov rax, dr0
|
||||
push rax
|
||||
|
||||
;; FX_SAVE_STATE_X64 FxSaveState;
|
||||
sub rsp, 512
|
||||
mov rdi, rsp
|
||||
db 0fh, 0aeh, 07h ;fxsave [rdi]
|
||||
|
||||
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
|
||||
cld
|
||||
|
||||
;; UINT32 ExceptionData;
|
||||
push qword ptr [rbp + 16]
|
||||
|
||||
;; Prepare parameter and call
|
||||
mov rcx, [rbp + 8]
|
||||
mov rdx, rsp
|
||||
;
|
||||
; Per X64 calling convention, allocate maximum parameter stack space
|
||||
; and make sure RSP is 16-byte aligned
|
||||
;
|
||||
sub rsp, 4 * 8 + 8
|
||||
mov rax, CommonExceptionHandler
|
||||
call rax
|
||||
add rsp, 4 * 8 + 8
|
||||
|
||||
cli
|
||||
;; UINT64 ExceptionData;
|
||||
add rsp, 8
|
||||
|
||||
;; FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
mov rsi, rsp
|
||||
db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
|
||||
add rsp, 512
|
||||
|
||||
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
;; Skip restoration of DRx registers to support in-circuit emualators
|
||||
;; or debuggers set breakpoint in interrupt/exception context
|
||||
add rsp, 8 * 6
|
||||
|
||||
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
pop rax
|
||||
mov cr0, rax
|
||||
add rsp, 8 ; not for Cr1
|
||||
pop rax
|
||||
mov cr2, rax
|
||||
pop rax
|
||||
mov cr3, rax
|
||||
pop rax
|
||||
mov cr4, rax
|
||||
pop rax
|
||||
mov cr8, rax
|
||||
|
||||
;; UINT64 RFlags;
|
||||
pop qword ptr [rbp + 40]
|
||||
|
||||
;; UINT64 Ldtr, Tr;
|
||||
;; UINT64 Gdtr[2], Idtr[2];
|
||||
;; Best not let anyone mess with these particular registers...
|
||||
add rsp, 48
|
||||
|
||||
;; UINT64 Rip;
|
||||
pop qword ptr [rbp + 24]
|
||||
|
||||
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
pop rax
|
||||
; mov gs, rax ; not for gs
|
||||
pop rax
|
||||
; mov fs, rax ; not for fs
|
||||
; (X64 will not use fs and gs, so we do not restore it)
|
||||
pop rax
|
||||
mov es, rax
|
||||
pop rax
|
||||
mov ds, rax
|
||||
pop qword ptr [rbp + 32] ; for cs
|
||||
pop qword ptr [rbp + 56] ; for ss
|
||||
|
||||
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
pop rdi
|
||||
pop rsi
|
||||
add rsp, 8 ; not for rbp
|
||||
pop qword ptr [rbp + 48] ; for rsp
|
||||
pop rbx
|
||||
pop rdx
|
||||
pop rcx
|
||||
pop rax
|
||||
pop r8
|
||||
pop r9
|
||||
pop r10
|
||||
pop r11
|
||||
pop r12
|
||||
pop r13
|
||||
pop r14
|
||||
pop r15
|
||||
|
||||
mov rsp, rbp
|
||||
pop rbp
|
||||
add rsp, 16
|
||||
iretq
|
||||
|
||||
CommonInterruptEntry ENDP
|
||||
|
||||
;-------------------------------------------------------------------------------------
|
||||
; GetTemplateAddressMap (&AddressMap);
|
||||
;-------------------------------------------------------------------------------------
|
||||
; comments here for definition of address map
|
||||
GetTemplateAddressMap PROC
|
||||
mov rax, offset Exception0Handle
|
||||
mov qword ptr [rcx], rax
|
||||
mov qword ptr [rcx+8h], Exception1Handle - Exception0Handle
|
||||
ret
|
||||
GetTemplateAddressMap ENDP
|
||||
|
||||
END
|
||||
Reference in New Issue
Block a user