CryptoPkg: Add RISC-V architecture for EDK2 CI.

Add RISC-V architecture for EDK2 CI testing.

BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Xiaoyu Lu <xiaoyux.lu@intel.com>

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
This commit is contained in:
Abner Chang
2020-03-27 11:08:01 +08:00
committed by mergify[bot]
parent 0a44fd3165
commit 9025a014f9
11 changed files with 27 additions and 10 deletions

View File

@@ -7,6 +7,7 @@
# buffer overflow or integer overflow.
#
# Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -23,7 +24,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
#
[Sources]