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1. Impl PI 1.2 PCI part. Major changes include:

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a. Update PciBusDxe module, and move it from IntelFrameworkModulePkg to MdeModulePkg
  b. Move IncompatiblePciDeviceSupportDxe module from IntelFrameworkModulePkg to MdeModulePkg
  c. Update the related consumes in inf/dsc/fdf

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9347 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
davidhuang
2009-10-20 03:43:40 +00:00
parent d47bdf8499
commit 9060e3ec6d
33 changed files with 18148 additions and 0 deletions
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248
MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c Normal file
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/** @file
PCI command register operations supporting functions implementation for PCI Bus module.
Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PciBus.h"
/**
Operate the PCI register via PciIo function interface.
@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
@param Command Operator command.
@param Offset The address within the PCI configuration space for the PCI controller.
@param Operation Type of Operation.
@param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.
@return Status of PciIo operation.
**/
EFI_STATUS
PciOperateRegister (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
)
{
UINT16 OldCommand;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
OldCommand = 0;
PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) {
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
if (Operation == EFI_GET_REGISTER) {
*PtrCommand = OldCommand;
return Status;
}
}
if (Operation == EFI_ENABLE_REGISTER) {
OldCommand = (UINT16) (OldCommand | Command);
} else if (Operation == EFI_DISABLE_REGISTER) {
OldCommand = (UINT16) (OldCommand & ~(Command));
} else {
OldCommand = Command;
}
return PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
}
/**
Check the cpability supporting by given device.
@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
@retval TRUE Cpability supportted.
@retval FALSE Cpability not supportted.
**/
BOOLEAN
PciCapabilitySupport (
IN PCI_IO_DEVICE *PciIoDevice
)
{
if ((PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) != 0) {
return TRUE;
}
return FALSE;
}
/**
Locate capability register block per capability ID.
@param PciIoDevice A pointer to the PCI_IO_DEVICE.
@param CapId The capability ID.
@param Offset A pointer to the offset returned.
@param NextRegBlock A pointer to the next block returned.
@retval EFI_SUCCESS Successfuly located capability register block.
@retval EFI_UNSUPPORTED Pci device does not support capability.
@retval EFI_NOT_FOUND Pci device support but can not find register block.
**/
EFI_STATUS
LocateCapabilityRegBlock (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 CapId,
IN OUT UINT8 *Offset,
OUT UINT8 *NextRegBlock OPTIONAL
)
{
UINT8 CapabilityPtr;
UINT16 CapabilityEntry;
UINT8 CapabilityID;
//
// To check the cpability of this device supports
//
if (!PciCapabilitySupport (PciIoDevice)) {
return EFI_UNSUPPORTED;
}
if (*Offset != 0) {
CapabilityPtr = *Offset;
} else {
CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1,
&CapabilityPtr
);
} else {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
PCI_CAPBILITY_POINTER_OFFSET,
1,
&CapabilityPtr
);
}
}
while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
CapabilityPtr,
1,
&CapabilityEntry
);
CapabilityID = (UINT8) CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;
if (NextRegBlock != NULL) {
*NextRegBlock = (UINT8) (CapabilityEntry >> 8);
}
return EFI_SUCCESS;
}
CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
}
return EFI_NOT_FOUND;
}
/**
Locate PciExpress capability register block per capability ID.
@param PciIoDevice A pointer to the PCI_IO_DEVICE.
@param CapId The capability ID.
@param Offset A pointer to the offset returned.
@param NextRegBlock A pointer to the next block returned.
@retval EFI_SUCCESS Successfuly located capability register block.
@retval EFI_UNSUPPORTED Pci device does not support capability.
@retval EFI_NOT_FOUND Pci device support but can not find register block.
**/
EFI_STATUS
LocatePciExpressCapabilityRegBlock (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
)
{
UINT32 CapabilityPtr;
UINT32 CapabilityEntry;
UINT16 CapabilityID;
//
// To check the capability of this device supports
//
if (!PciIoDevice->IsPciExp) {
return EFI_UNSUPPORTED;
}
if (*Offset != 0) {
CapabilityPtr = *Offset;
} else {
CapabilityPtr = EFI_PCIE_CAPABILITY_BASE_OFFSET;
}
while (CapabilityPtr != 0) {
//
// Mask it to DWORD alignment per PCI spec
//
CapabilityPtr &= 0xFFC;
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint32,
CapabilityPtr,
1,
&CapabilityEntry
);
CapabilityID = (UINT16) CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;
if (NextRegBlock != NULL) {
*NextRegBlock = (CapabilityEntry >> 20) & 0xFFF;
}
return EFI_SUCCESS;
}
CapabilityPtr = (CapabilityEntry >> 20) & 0xFFF;
}
return EFI_NOT_FOUND;
}