Import EhciDxe and UhciDxe into MdeModulePkg.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3191 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
303
MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
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303
MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
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/** @file
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Copyright (c) 2007, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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UhciReg.c
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Abstract:
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The UHCI register operation routines.
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Revision History
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**/
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#include "Uhci.h"
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/**
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Read a UHCI register
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@param PciIo The EFI_PCI_IO_PROTOCOL to use
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@param Offset Register offset to USB_BAR_INDEX
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@return Content of register
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**/
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UINT16
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UhciReadReg (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset
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)
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{
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UINT16 Data;
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EFI_STATUS Status;
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Status = PciIo->Io.Read (
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PciIo,
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EfiPciIoWidthUint16,
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USB_BAR_INDEX,
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Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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UHCI_ERROR (("UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));
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Data = 0xFFFF;
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}
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return Data;
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}
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/**
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Write data to UHCI register
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@param PciIo The EFI_PCI_IO_PROTOCOL to use
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@param Offset Register offset to USB_BAR_INDEX
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@param Data Data to write
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@return VOID
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**/
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VOID
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UhciWriteReg (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset,
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IN UINT16 Data
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)
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{
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EFI_STATUS Status;
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Status = PciIo->Io.Write (
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PciIo,
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EfiPciIoWidthUint16,
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USB_BAR_INDEX,
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Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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UHCI_ERROR (("UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));
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}
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}
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/**
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Set a bit of the UHCI Register
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@param PciIo The EFI_PCI_IO_PROTOCOL to use
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@param Offset Register offset to USB_BAR_INDEX
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@param Bit The bit to set
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@return None
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**/
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VOID
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UhciSetRegBit (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset,
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IN UINT16 Bit
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)
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{
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UINT16 Data;
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Data = UhciReadReg (PciIo, Offset);
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Data |= Bit;
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UhciWriteReg (PciIo, Offset, Data);
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}
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/**
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Clear a bit of the UHCI Register
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@param PciIo The PCI_IO protocol to access the PCI
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@param Offset Register offset to USB_BAR_INDEX
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@param Bit The bit to clear
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@return None
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**/
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VOID
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UhciClearRegBit (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset,
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IN UINT16 Bit
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)
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{
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UINT16 Data;
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Data = UhciReadReg (PciIo, Offset);
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Data &= ~Bit;
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UhciWriteReg (PciIo, Offset, Data);
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}
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/**
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Clear all the interrutp status bits, these bits
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are Write-Clean
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@param Uhc The UHCI device
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@return None
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**/
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VOID
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UhciAckAllInterrupt (
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IN USB_HC_DEV *Uhc
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)
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{
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UhciWriteReg (Uhc->PciIo, USBSTS_OFFSET, 0x3F);
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//
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// If current HC is halted, re-enable it. Host Controller Process Error
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// is a temporary error status.
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//
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if (!UhciIsHcWorking (Uhc->PciIo)) {
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UHCI_ERROR (("UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
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Uhc->UsbHc.SetState (&Uhc->UsbHc, EfiUsbHcStateOperational);
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}
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}
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/**
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Stop the host controller
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@param Uhc The UHCI device
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@param Timeout Max time allowed
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@retval EFI_SUCCESS The host controller is stopped
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@retval EFI_TIMEOUT Failed to stop the host controller
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**/
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EFI_STATUS
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UhciStopHc (
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IN USB_HC_DEV *Uhc,
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IN UINTN Timeout
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)
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{
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UINT16 UsbSts;
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UINTN Index;
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UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_RS);
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//
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// ensure the HC is in halt status after send the stop command
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// Timeout is in us unit.
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//
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for (Index = 0; Index < (Timeout / 50) + 1; Index++) {
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UsbSts = UhciReadReg (Uhc->PciIo, USBSTS_OFFSET);
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if ((UsbSts & USBSTS_HCH) == USBSTS_HCH) {
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return EFI_SUCCESS;
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}
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gBS->Stall (50);
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}
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return EFI_TIMEOUT;
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}
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/**
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Check whether the host controller operates well
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@param PciIo The PCI_IO protocol to use
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@retval TRUE Host controller is working
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@retval FALSE Host controller is halted or system error
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**/
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BOOLEAN
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UhciIsHcWorking (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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UINT16 UsbSts;
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UsbSts = UhciReadReg (PciIo, USBSTS_OFFSET);
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if (UsbSts & (USBSTS_HCPE | USBSTS_HSE | USBSTS_HCH)) {
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UHCI_ERROR (("UhciIsHcWorking: current USB state is %x\n", UsbSts));
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return FALSE;
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}
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return TRUE;
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}
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/**
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Set the UHCI frame list base address. It can't use
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UhciWriteReg which access memory in UINT16.
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@param PciIo The EFI_PCI_IO_PROTOCOL to use
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@param Addr Address to set
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@return VOID
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**/
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VOID
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UhciSetFrameListBaseAddr (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN VOID *Addr
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)
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{
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EFI_STATUS Status;
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UINT32 Data;
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Data = (UINT32) ((UINTN) Addr & 0xFFFFF000);
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Status = PciIo->Io.Write (
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PciIo,
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EfiPciIoWidthUint32,
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USB_BAR_INDEX,
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(UINT64) USB_FRAME_BASE_OFFSET,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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UHCI_ERROR (("UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status));
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}
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}
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/**
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Disable USB Emulation
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@param PciIo The EFI_PCI_IO_PROTOCOL protocol to use
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@return VOID
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**/
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VOID
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UhciTurnOffUsbEmulation (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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UINT16 Command;
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Command = 0;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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USB_EMULATION_OFFSET,
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1,
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&Command
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);
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}
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