IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspWrapperPlatformSecLibSample support for X64. 2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample. 3.Moved Fsp.h up one level to be shared across IA32 and X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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@@ -1,45 +0,0 @@
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/** @file
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Fsp related definitions
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Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __FSP_H__
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#define __FSP_H__
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//
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// Fv Header
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//
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#define FVH_FV_LENGTH_OFFSET 0x20
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#define FVH_SIGINATURE_OFFSET 0x28
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#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
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#define FVH_HEADER_LENGTH_OFFSET 0x30
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#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
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#define FVH_EXTHEADER_SIZE_OFFSET 0x10
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//
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// Ffs Header
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//
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#define FSP_HEADER_SIGNATURE_OFFSET 0x1C
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#define FSP_HEADER_SIGNATURE 0x48505346 ; valid signature:FSPH
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#define FSP_HEADER_GUID_DWORD1 0x912740BE
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#define FSP_HEADER_GUID_DWORD2 0x47342284
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#define FSP_HEADER_GUID_DWORD3 0xB08471B9
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#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
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#define FFS_HEADER_SIZE_VALUE 0x18
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//
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// Section Header
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//
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#define SECTION_HEADER_TYPE_OFFSET 0x03
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#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
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//
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// Fsp Header
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//
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#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
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#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
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#endif
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@@ -1,6 +1,6 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Abstract:
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@@ -22,7 +22,7 @@
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global ASM_PFX(SecSwitchStack)
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ASM_PFX(SecSwitchStack):
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;
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; Save three register: eax, ebx, ecx
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; Save four register: eax, ebx, ecx, edx
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;
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push eax
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push ebx
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@@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack):
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mov dword [eax + 12], edx
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mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
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mov dword [eax + 16], edx
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mov esp, eax ; From now, esp is pointed to permanent memory
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mov esp, eax ; From now, esp is pointed to permanent memory
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;
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; Fixup the ebp point to permanent memory
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@@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack):
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mov eax, ebp
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sub eax, ebx
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add eax, ecx
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mov ebp, eax ; From now, ebp is pointed to permanent memory
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mov ebp, eax ; From now, ebp is pointed to permanent memory
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pop edx
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pop ecx
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