IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspWrapperPlatformSecLibSample support for X64. 2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample. 3.Moved Fsp.h up one level to be shared across IA32 and X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Ted Kuo
mergify[bot]
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; PeiCoreEntry.nasm
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;
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; Abstract:
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;
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; Find and call SecStartup
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;
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;------------------------------------------------------------------------------
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SECTION .text
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%include "PushPopRegsNasm.inc"
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extern ASM_PFX(SecStartup)
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extern ASM_PFX(PlatformInit)
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;
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; args 1:XMM, 2:REG, 3:IDX
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;
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%macro LXMMN 3
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pextrq %2, %1, (%3 & 3)
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%endmacro
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;
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; args 1:YMM, 2:XMM, 3:IDX (0 - lower 128bits, 1 - upper 128bits)
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;
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%macro LYMMN 3
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vextractf128 %2, %1, %3
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%endmacro
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%macro LOAD_TS 1
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LYMMN ymm6, xmm5, 1
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LXMMN xmm5, %1, 1
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%endmacro
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global ASM_PFX(CallPeiCoreEntryPoint)
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ASM_PFX(CallPeiCoreEntryPoint):
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;
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; Per X64 calling convention, make sure RSP is 16-byte aligned.
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;
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mov rax, rsp
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and rax, 0fh
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sub rsp, rax
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;
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; Platform init
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;
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PUSHA_64
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sub rsp, 20h
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call ASM_PFX(PlatformInit)
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add rsp, 20h
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POPA_64
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;
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; Set stack top pointer
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;
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mov rsp, r8
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;
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; Push the hob list pointer
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;
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push rcx
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;
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; RBP holds start of BFV passed from Vtf0. Save it to r10.
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;
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mov r10, rbp
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;
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; Save the value
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; RDX: start of range
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; r8: end of range
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;
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mov rbp, rsp
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push rdx
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push r8
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mov r14, rdx
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mov r15, r8
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;
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; Push processor count to stack first, then BIST status (AP then BSP)
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;
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mov eax, 1
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cpuid
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shr ebx, 16
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and ebx, 0000000FFh
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cmp bl, 1
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jae PushProcessorCount
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;
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; Some processors report 0 logical processors. Effectively 0 = 1.
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; So we fix up the processor count
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;
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inc ebx
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PushProcessorCount:
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sub rsp, 4
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mov rdi, rsp
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mov DWORD [rdi], ebx
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;
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; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
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; for all processor threads
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;
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xor ecx, ecx
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mov cl, bl
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PushBist:
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sub rsp, 4
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mov rdi, rsp
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movd eax, mm0
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mov DWORD [rdi], eax
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loop PushBist
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; Save Time-Stamp Counter
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LOAD_TS rax
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push rax
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;
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; Pass entry point of the PEI core
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;
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mov rdi, 0FFFFFFE0h
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mov edi, DWORD [rdi]
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mov r9, rdi
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;
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; Pass BFV into the PEI Core
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;
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mov r8, r10
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;
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; Pass stack size into the PEI Core
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;
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mov rcx, r15 ; Start of TempRam
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mov rdx, r14 ; End of TempRam
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sub rcx, rdx ; Size of TempRam
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;
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; Pass Control into the PEI Core
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;
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sub rsp, 20h
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call ASM_PFX(SecStartup)
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@@ -0,0 +1,171 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; SecEntry.asm
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;
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; Abstract:
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;
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; This is the code that calls TempRamInit API from FSP binary and passes
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; control into PEI core.
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;
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;------------------------------------------------------------------------------
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#include "Fsp.h"
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IA32_CR4_OSFXSR equ 200h
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IA32_CR4_OSXMMEXCPT equ 400h
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IA32_CR0_MP equ 2h
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IA32_CPUID_SSE2 equ 02000000h
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IA32_CPUID_SSE2_B equ 26
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SECTION .text
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extern ASM_PFX(CallPeiCoreEntryPoint)
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extern ASM_PFX(FsptUpdDataPtr)
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; Pcds
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extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
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;----------------------------------------------------------------------------
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;
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; Procedure: _ModuleEntryPoint
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;
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; Input: None
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;
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; Output: None
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;
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; Destroys: Assume all registers
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;
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; Description:
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;
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; Call TempRamInit API from FSP binary. After TempRamInit done, pass
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; control into PEI core.
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;
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; Return: None
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;
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; MMX Usage:
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; MM0 = BIST State
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;
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;----------------------------------------------------------------------------
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BITS 64
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align 16
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global ASM_PFX(ModuleEntryPoint)
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ASM_PFX(ModuleEntryPoint):
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fninit ; clear any pending Floating point exceptions
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;
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; Store the BIST value in mm0
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;
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movd mm0, eax
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; Find the fsp info header
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mov rax, ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
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mov edi, [eax]
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mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
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cmp eax, FVH_SIGINATURE_VALID_VALUE
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jnz FspHeaderNotFound
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xor eax, eax
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mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
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cmp ax, 0
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jnz FspFvExtHeaderExist
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xor eax, eax
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mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
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add edi, eax
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jmp FspCheckFfsHeader
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FspFvExtHeaderExist:
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add edi, eax
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mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
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add edi, eax
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; Round up to 8 byte alignment
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mov eax, edi
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and al, 07h
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jz FspCheckFfsHeader
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and edi, 0FFFFFFF8h
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add edi, 08h
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FspCheckFfsHeader:
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; Check the ffs guid
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mov eax, dword [edi]
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cmp eax, FSP_HEADER_GUID_DWORD1
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jnz FspHeaderNotFound
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mov eax, dword [edi + 4]
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cmp eax, FSP_HEADER_GUID_DWORD2
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jnz FspHeaderNotFound
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mov eax, dword [edi + 8]
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cmp eax, FSP_HEADER_GUID_DWORD3
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jnz FspHeaderNotFound
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mov eax, dword [edi + 0Ch]
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cmp eax, FSP_HEADER_GUID_DWORD4
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jnz FspHeaderNotFound
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add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
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; Check the section type as raw section
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mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
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cmp al, 019h
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jnz FspHeaderNotFound
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add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
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jmp FspHeaderFound
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FspHeaderNotFound:
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jmp $
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FspHeaderFound:
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; Get the fsp TempRamInit Api address
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mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
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add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
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; Setup the hardcode stack
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mov rsp, TempRamInitStack
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; Call the fsp TempRamInit Api
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jmp rax
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TempRamInitDone:
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cmp rax, 0800000000000000Eh ; Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
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je CallSecFspInit ; If microcode not found, don't hang, but continue.
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cmp rax, 0 ; Check if EFI_SUCCESS returned.
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jnz FspApiFailed
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; RDX: start of range
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; R8: end of range
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CallSecFspInit:
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mov r8, rdx
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mov rdx, rcx
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xor ecx, ecx ; zero - no Hob List Yet
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mov rsp, r8
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;
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; Per X64 calling convention, make sure RSP is 16-byte aligned.
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;
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mov rax, rsp
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and rax, 0fh
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sub rsp, rax
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call ASM_PFX(CallPeiCoreEntryPoint)
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FspApiFailed:
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jmp $
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align 10h
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TempRamInitStack:
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DQ TempRamInitDone
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DQ ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams
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@@ -0,0 +1,73 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Abstract:
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;
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; Switch the stack from temporary memory to permanent memory.
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;
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;------------------------------------------------------------------------------
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SECTION .text
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;------------------------------------------------------------------------------
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; VOID
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; EFIAPI
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; SecSwitchStack (
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; UINT32 TemporaryMemoryBase,
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; UINT32 PermanentMemoryBase
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(SecSwitchStack)
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ASM_PFX(SecSwitchStack):
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;
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; Save four register: rax, rbx, rcx, rdx
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;
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push rax
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push rbx
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push rcx
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push rdx
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;
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; !!CAUTION!! this function address's is pushed into stack after
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; migration of whole temporary memory, so need save it to permanent
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; memory at first!
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;
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mov rbx, rcx ; Save the first parameter
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mov rcx, rdx ; Save the second parameter
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;
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; Save this function's return address into permanent memory at first.
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; Then, Fixup the esp point to permanent memory
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;
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mov rax, rsp
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sub rax, rbx
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add rax, rcx
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mov rdx, qword [rsp] ; copy pushed register's value to permanent memory
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mov qword [rax], rdx
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mov rdx, qword [rsp + 8]
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mov qword [rax + 8], rdx
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mov rdx, qword [rsp + 16]
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mov qword [rax + 16], rdx
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mov rdx, qword [rsp + 24]
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mov qword [rax + 24], rdx
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mov rdx, qword [rsp + 32] ; Update this function's return address into permanent memory
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mov qword [rax + 32], rdx
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mov rsp, rax ; From now, rsp is pointed to permanent memory
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;
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; Fixup the rbp point to permanent memory
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;
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mov rax, rbp
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sub rax, rbx
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add rax, rcx
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mov rbp, rax ; From now, rbp is pointed to permanent memory
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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