ARM Packages: Replace tabs by spaces for indentation
Replace tabs by spaces for indentation to comply to EDK2 coding standards. Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf", "*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg, BeagleBoardPkg or Omap35xxPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
committed by
oliviermartin
oliviermartin
parent
5c670b2119
commit
91c38d4e94
@@ -17,36 +17,36 @@
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typedef struct {
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UINTN HasQos; // has QoS registers
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UINTN MaxChip; // number of memory chips accessible
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BOOLEAN IsUserCfg;
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UINTN HasQos; // has QoS registers
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UINTN MaxChip; // number of memory chips accessible
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BOOLEAN IsUserCfg;
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UINT32 User0Cfg;
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UINT32 User2Cfg;
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UINT32 RefreshPeriod;
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UINT32 CasLatency;
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UINT32 WriteLatency;
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UINT32 t_mrd;
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UINT32 t_ras;
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UINT32 t_rc;
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UINT32 t_rcd;
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UINT32 t_rfc;
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UINT32 t_rp;
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UINT32 t_rrd;
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UINT32 t_wr;
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UINT32 t_wtr;
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UINT32 t_xp;
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UINT32 t_xsr;
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UINT32 t_esr;
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UINT32 MemoryCfg;
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UINT32 MemoryCfg2;
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UINT32 MemoryCfg3;
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UINT32 ChipCfg0;
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UINT32 ChipCfg1;
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UINT32 ChipCfg2;
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UINT32 ChipCfg3;
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UINT32 t_faw;
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UINT32 t_data_en;
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UINT32 t_wdata_en;
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UINT32 RefreshPeriod;
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UINT32 CasLatency;
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UINT32 WriteLatency;
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UINT32 t_mrd;
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UINT32 t_ras;
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UINT32 t_rc;
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UINT32 t_rcd;
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UINT32 t_rfc;
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UINT32 t_rp;
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UINT32 t_rrd;
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UINT32 t_wr;
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UINT32 t_wtr;
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UINT32 t_xp;
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UINT32 t_xsr;
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UINT32 t_esr;
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UINT32 MemoryCfg;
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UINT32 MemoryCfg2;
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UINT32 MemoryCfg3;
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UINT32 ChipCfg0;
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UINT32 ChipCfg1;
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UINT32 ChipCfg2;
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UINT32 ChipCfg3;
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UINT32 t_faw;
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UINT32 t_data_en;
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UINT32 t_wdata_en;
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UINT32 ModeReg;
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UINT32 ExtModeReg;
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} PL341_DMC_CONFIG;
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@@ -107,7 +107,7 @@ typedef struct {
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#define DMC_MEMORY_CFG2_REG 0x4C
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#define DMC_MEMORY_CFG3_REG 0x50
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#define DMC_T_FAW_REG 0x54
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#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
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#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
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#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
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// Returns the state of the memory controller:
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@@ -182,66 +182,66 @@ typedef struct {
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//
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// PHY Register Settings
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//
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#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
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#define PHY_PTM_IOTERM 0xE04
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#define PHY_PTM_PLL_EN 0xe0c
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#define PHY_PTM_PLL_RANGE 0xe18
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#define PHY_PTM_FEEBACK_DIV 0xe1c
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#define PHY_PTM_RCLK_DIV 0xe20
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#define PHY_PTM_LOCK_STATUS 0xe28
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#define PHY_PTM_INIT_DONE 0xe34
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#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
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#define PHY_PTM_SQU_TRAINING 0xee8
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#define PHY_PTM_SQU_STAT 0xeec
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#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
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#define PHY_PTM_IOTERM 0xE04
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#define PHY_PTM_PLL_EN 0xe0c
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#define PHY_PTM_PLL_RANGE 0xe18
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#define PHY_PTM_FEEBACK_DIV 0xe1c
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#define PHY_PTM_RCLK_DIV 0xe20
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#define PHY_PTM_LOCK_STATUS 0xe28
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#define PHY_PTM_INIT_DONE 0xe34
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#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
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#define PHY_PTM_SQU_TRAINING 0xee8
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#define PHY_PTM_SQU_STAT 0xeec
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// ==============================================================================
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// PIPD 40G DDR2/DDR3 PHY Register definitions
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//
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// Offsets from APB Base Address
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// ==============================================================================
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#define PHY_BYTE0_OFFSET 0x000
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#define PHY_BYTE1_OFFSET 0x200
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#define PHY_BYTE2_OFFSET 0x400
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#define PHY_BYTE3_OFFSET 0x600
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#define PHY_BYTE0_OFFSET 0x000
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#define PHY_BYTE1_OFFSET 0x200
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#define PHY_BYTE2_OFFSET 0x400
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#define PHY_BYTE3_OFFSET 0x600
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#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
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#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
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#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
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#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
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#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
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#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
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#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
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#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
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#define PHY_BYTE0_IOSTR_OFFSET 0x004
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#define PHY_BYTE1_IOSTR_OFFSET 0x204
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#define PHY_BYTE2_IOSTR_OFFSET 0x404
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#define PHY_BYTE3_IOSTR_OFFSET 0x604
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#define PHY_BYTE0_IOSTR_OFFSET 0x004
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#define PHY_BYTE1_IOSTR_OFFSET 0x204
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#define PHY_BYTE2_IOSTR_OFFSET 0x404
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#define PHY_BYTE3_IOSTR_OFFSET 0x604
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;//--------------------------------------------------------------------------
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// DFI Clock ranges:
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#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
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#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
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#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
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#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
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#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
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#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
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#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
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#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
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#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
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#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
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#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
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#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
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#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
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#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
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#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
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#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
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//--------------------------------------------------------------------------
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// PLL Range
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#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
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#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
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#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
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#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
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#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
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#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
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#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
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#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
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#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
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#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
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#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
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#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
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#define TC_UIOLHNC_MASK 0x000003C0
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#define TC_UIOLHNC_SHIFT 0x6
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@@ -252,18 +252,18 @@ typedef struct {
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#define TC_UIOHSTOP_SHIFT 0x0
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#define TC_UIOLHXC_VALUE 0x4
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#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
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#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
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#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
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#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
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//--------------------------------------
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// JEDEC DDR2 Device Register definitions and settings
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//--------------------------------------
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#define DDR_MODESET_SHFT 14
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#define DDR_MODESET_MR 0x0 ;// Mode register
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#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
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#define DDR_MODESET_EMR2 0x2
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#define DDR_MODESET_EMR3 0x3
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#define DDR_MODESET_SHFT 14
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#define DDR_MODESET_MR 0x0 ;// Mode register
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#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
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#define DDR_MODESET_EMR2 0x2
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#define DDR_MODESET_EMR3 0x3
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//
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// Extended Mode Register settings
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@@ -290,21 +290,21 @@ typedef struct {
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#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
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#define DDR_SDRAM_START_ADDR 0x10000000
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#define DDR_SDRAM_START_ADDR 0x10000000
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// ----------------------------------------
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// PHY IOTERM values
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// ----------------------------------------
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#define PHY_PTM_IOTERM_OFF 0x0
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#define PHY_PTM_IOTERM_150R 0x1
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#define PHY_PTM_IOTERM_75R 0x2
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#define PHY_PTM_IOTERM_50R 0x3
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#define PHY_PTM_IOTERM_OFF 0x0
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#define PHY_PTM_IOTERM_150R 0x1
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#define PHY_PTM_IOTERM_75R 0x2
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#define PHY_PTM_IOTERM_50R 0x3
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#define PHY_BYTE_IOSTR_60OHM 0x0
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#define PHY_BYTE_IOSTR_40OHM 0x1
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#define PHY_BYTE_IOSTR_30OHM 0x2
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#define PHY_BYTE_IOSTR_30AOHM 0x3
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#define PHY_BYTE_IOSTR_60OHM 0x0
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#define PHY_BYTE_IOSTR_40OHM 0x1
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#define PHY_BYTE_IOSTR_30OHM 0x2
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#define PHY_BYTE_IOSTR_30AOHM 0x3
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#define DDR2_MR_BURST_LENGTH_4 (2)
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#define DDR2_MR_BURST_LENGTH_8 (3)
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