diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 9a3bc3a7b0..c12de9481b 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -65,8 +65,6 @@
   # it has been configured by the CPU DXE
   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
   
-  gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025
-
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
index e5709a63d0..9a3b8e8afc 100644
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
@@ -81,7 +81,6 @@
   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport
   gArmTokenSpaceGuid.PcdRelocateVectorTable
   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport
-  gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered
 
 [Depex]
   TRUE
diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index 6218b5d27f..f54350b5a2 100644
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -498,13 +498,8 @@ UpdatePageEntries (
     case EFI_MEMORY_UC:
       // modify cacheability attributes
       EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
-      if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
-        // map to strongly ordered
-        EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
-      } else {
-        // map to normal non-cachable
-        EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
-      }
+      // map to strongly ordered
+      EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
       break;
 
     case EFI_MEMORY_WC:
@@ -646,13 +641,8 @@ UpdateSectionEntries (
     case EFI_MEMORY_UC:
       // modify cacheability attributes
       EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
-      if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
-        // map to strongly ordered
-        EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
-      } else {
-        // map to normal non-cachable
-        EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
-      }
+      // map to strongly ordered
+      EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
       break;
 
     case EFI_MEMORY_WC: