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UefiCpuPkg: Change use of EFI_D_* to DEBUG_*

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3739

Update all use of EFI_D_* defines in DEBUG() macros to DEBUG_* defines.

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael D Kinney
2021-11-16 19:21:42 -08:00
committed by mergify[bot]
parent 586fda4800
commit 96e1cba5c1
10 changed files with 56 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
View File

@@ -751,7 +751,7 @@ SmmRestoreCpu (
IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
EFI_STATUS Status;
DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));
DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n"));
mSmmS3Flag = TRUE;
@@ -759,7 +759,7 @@ SmmRestoreCpu (
// See if there is enough context to resume PEI Phase
//
if (mSmmS3ResumeState == NULL) {
DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
DEBUG ((DEBUG_ERROR, "No context to return to PEI Phase\n"));
CpuDeadLoop ();
}
@@ -822,17 +822,17 @@ SmmRestoreCpu (
//
mRestoreSmmConfigurationInS3 = TRUE;
DEBUG (( EFI_D_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
DEBUG (( EFI_D_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
DEBUG (( EFI_D_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
DEBUG (( DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
DEBUG (( DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
DEBUG (( DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
//
// If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
//
if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
@@ -846,7 +846,7 @@ SmmRestoreCpu (
// If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
//
if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
DEBUG ((DEBUG_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
//
// Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
//
@@ -867,7 +867,7 @@ SmmRestoreCpu (
//
// Can not resume PEI Phase
//
DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
DEBUG ((DEBUG_ERROR, "No context to return to PEI Phase\n"));
CpuDeadLoop ();
}
@@ -904,8 +904,8 @@ InitSmmS3ResumeState (
} else {
SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
DEBUG ((EFI_D_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));

4
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@@ -1788,8 +1788,8 @@ InitializeSmmCpuSemaphores (
GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * SemaphoreSize;
CpuSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) * ProcessorCount * SemaphoreSize;
TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize;
DEBUG((EFI_D_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize));
DEBUG((EFI_D_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));
DEBUG((DEBUG_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize));
DEBUG((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));
Pages = EFI_SIZE_TO_PAGES (TotalSize);
SemaphoreBlock = AllocatePages (Pages);
ASSERT (SemaphoreBlock != NULL);

14
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@@ -608,14 +608,14 @@ PiCpuSmmEntry (
// Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
//
mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);
DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));
DEBUG ((DEBUG_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));
//
// Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.
// Make sure AddressEncMask is contained to smallest supported address field.
//
mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
DEBUG ((EFI_D_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));
DEBUG ((DEBUG_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));
//
// If support CPU hot plug, we need to allocate resources for possibly hot-added processors
@@ -767,7 +767,7 @@ PiCpuSmmEntry (
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
//
// If the TileSize is larger than space available for the SMI Handler of
@@ -797,7 +797,7 @@ PiCpuSmmEntry (
Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
}
ASSERT (Buffer != NULL);
DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));
DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));
//
// Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
@@ -842,7 +842,7 @@ PiCpuSmmEntry (
ASSERT_EFI_ERROR (Status);
mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
DEBUG ((EFI_D_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
DEBUG ((DEBUG_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
Index,
(UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
mCpuHotPlugData.SmBase[Index],
@@ -1072,7 +1072,7 @@ PiCpuSmmEntry (
GetAcpiS3EnableFlag ();
InitSmmS3ResumeState (Cr3);
DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
DEBUG ((DEBUG_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
return EFI_SUCCESS;
}
@@ -1162,7 +1162,7 @@ FindSmramInfo (
}
} while (Found);
DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));
DEBUG ((DEBUG_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));
}
/**

16
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
View File

@@ -514,14 +514,14 @@ InitProtectedMemRange (
mSplitMemRangeCount = NumberOfSpliteRange;
DEBUG ((EFI_D_INFO, "SMM Profile Memory Ranges:\n"));
DEBUG ((DEBUG_INFO, "SMM Profile Memory Ranges:\n"));
for (Index = 0; Index < mProtectionMemRangeCount; Index++) {
DEBUG ((EFI_D_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));
DEBUG ((EFI_D_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top));
DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));
DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top));
}
for (Index = 0; Index < mSplitMemRangeCount; Index++) {
DEBUG ((EFI_D_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));
DEBUG ((EFI_D_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top));
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top));
}
}
@@ -671,7 +671,7 @@ InitPaging (
//
// Go through page table and set several page table entries to absent or execute-disable.
//
DEBUG ((EFI_D_INFO, "Patch page table start ...\n"));
DEBUG ((DEBUG_INFO, "Patch page table start ...\n"));
for (Pml5Index = 0; Pml5Index < NumberOfPml5Entries; Pml5Index++) {
if ((Pml5[Pml5Index] & IA32_PG_P) == 0) {
//
@@ -760,7 +760,7 @@ InitPaging (
// Flush TLB
//
CpuFlushTlb ();
DEBUG ((EFI_D_INFO, "Patch page table done!\n"));
DEBUG ((DEBUG_INFO, "Patch page table done!\n"));
//
// Set execute-disable flag
//
@@ -786,7 +786,7 @@ GetSmiCommandPort (
ASSERT (Fadt != NULL);
mSmiCommandPort = Fadt->SmiCmd;
DEBUG ((EFI_D_INFO, "mSmiCommandPort = %x\n", mSmiCommandPort));
DEBUG ((DEBUG_INFO, "mSmiCommandPort = %x\n", mSmiCommandPort));
}
/**