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1. Added EdkPciIncompatibleDeviceSupportLib in EdkModulePkg, this library is used for PciBus driver and includes 3 Incompatible device lists.

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2. Used EdkPciIncompatibleDeviceSupportLib in PciBus driver. 
3. Redirect all Pci Configuration access to new APIs added in PciLib.c for PciBus driver.
4. Added one PCD PcdIncompatibleDeviceSupportMask in EdkModulePkg.spd to provide mask of PCI devices incompatibility check.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2562 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
2007-04-12 09:07:01 +00:00
parent 0eaa1933bc
commit 98419ef4b9
18 changed files with 2226 additions and 412 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa
View File

@@ -57,6 +57,9 @@
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PcdLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PciIncompatibleDeviceSupportLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>pcibus.h</Filename>
@@ -174,5 +177,10 @@
<DefaultValue>TRUE</DefaultValue>
<HelpText>If TRUE, the PCI bus driver will support hot plug device. If not hot plug device is supported, this feature flag can be set to FALSE to save size.</HelpText>
</PcdEntry>
<PcdEntry PcdItemType="FIXED_AT_BUILD" Usage="ALWAYS_CONSUMED">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>The PCD masks for PCI incompatible devices support</HelpText>
</PcdEntry>
</PcdCoded>
</ModuleSurfaceArea>

82
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.c
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciCommand.c
Abstract:
PCI Bus Driver
@@ -56,13 +56,13 @@ Returns:
PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) {
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
Status = PciIoRead (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
if (Operation == EFI_GET_REGISTER) {
*PtrCommand = OldCommand;
@@ -78,13 +78,13 @@ Returns:
OldCommand = Command;
}
return PciIo->Pci.Write (
return PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
);
}
BOOLEAN
@@ -98,7 +98,7 @@ Routine Description:
Arguments:
Returns:
None
--*/
@@ -131,7 +131,7 @@ Arguments:
NextRegBlock - A pointer to the next block.
Returns:
None
--*/
@@ -157,22 +157,22 @@ Returns:
CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1,
&CapabilityPtr
);
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1,
&CapabilityPtr
);
} else {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CAPABILITY_PTR,
1,
&CapabilityPtr
);
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CAPABILITY_PTR,
1,
&CapabilityPtr
);
}
}
@@ -181,13 +181,13 @@ Returns:
// Mask it to DWORD alignment per PCI spec
//
CapabilityPtr &= 0xFC;
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
CapabilityPtr,
1,
&CapabilityEntry
);
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
CapabilityPtr,
1,
&CapabilityEntry
);
CapabilityID = (UINT8) CapabilityEntry;

7
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c
View File

@@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -335,14 +335,13 @@ Returns:
if (!EFI_ERROR (Status)) {
PciIoDevice->IsPciExp = TRUE;
}
//
// Force Interrupt line to "Unknown" or "No Connection"
//
PciIo = &(PciIoDevice->PciIo);
Data8 = PCI_INT_LINE_UNKNOWN;
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
//
// Process Platform OpRom

94
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumerator.c
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciEnumerator.c
Abstract:
PCI Bus Driver
@@ -34,7 +34,7 @@ PciEnumerator (
Routine Description:
This routine is used to enumerate entire pci bus system
This routine is used to enumerate entire pci bus system
in a given platform
Arguments:
@@ -118,7 +118,7 @@ Returns:
if (EFI_ERROR (Status)) {
return Status;
}
//
// Submit the resource request
//
@@ -127,7 +127,7 @@ Returns:
if (EFI_ERROR (Status)) {
return Status;
}
//
// Process P2C
//
@@ -136,7 +136,7 @@ Returns:
if (EFI_ERROR (Status)) {
return Status;
}
//
// Process attributes for devices on this host bridge
//
@@ -286,7 +286,7 @@ Returns:
while (CurrentLink && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) {
//
// Go further to process the option rom under this bridge
//
@@ -294,7 +294,7 @@ Returns:
}
if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {
//
// Load and process the option rom
//
@@ -382,8 +382,9 @@ Returns:
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint16,
Address,
1,
@@ -394,8 +395,9 @@ Returns:
// Initialize SubBusNumber to SecondBus
//
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@@ -407,8 +409,9 @@ Returns:
if (IS_PCI_BRIDGE (&Pci)) {
Register8 = 0xFF;
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@@ -432,8 +435,9 @@ Returns:
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@@ -503,7 +507,7 @@ Returns:
// Here is the point where PCI bus driver calls HOST bridge allocation protocol
// Currently we hardcoded for ea815
//
if (Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) {
RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;
}
@@ -526,7 +530,7 @@ GetMaxOptionRomSize (
/*++
Routine Description:
Get Max Option Rom size on this bridge
Arguments:
@@ -552,7 +556,7 @@ Returns:
while (CurrentLink && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) {
//
// Get max option rom size under this bridge
//
@@ -567,13 +571,13 @@ Returns:
}
} else {
//
// For devices get the rom size directly
//
TempOptionRomSize = Temp->RomSize;
}
//
// Get the largest rom size on this bridge
//
@@ -594,7 +598,7 @@ PciHostBridgeDeviceAttribute (
/*++
Routine Description:
Process attributes of devices on this host bridge
Arguments:
@@ -650,7 +654,7 @@ GetResourceAllocationStatus (
/*++
Routine Description:
Get resource allocation status from the ACPI pointer
Arguments:
@@ -736,7 +740,7 @@ RejectPciDevice (
/*++
Routine Description:
Remove a PCI device from device pool and mark its bar
Arguments:
@@ -789,7 +793,7 @@ Returns:
//
InitializeP2C (PciDevice);
}
//
// Remove the device
//
@@ -817,7 +821,7 @@ IsRejectiveDevice (
/*++
Routine Description:
Determine whethter a PCI device can be rejected
Arguments:
@@ -839,7 +843,7 @@ Returns:
if (!Temp) {
return FALSE;
}
//
// PPB and RB should go ahead
//
@@ -853,7 +857,7 @@ Returns:
if ((Temp->Parent) && (Temp->BusNumber == 0)) {
return FALSE;
}
//
// Skip VGA
//
@@ -872,7 +876,7 @@ GetLargerConsumerDevice (
/*++
Routine Description:
Get the larger resource consumer
Arguments:
@@ -914,8 +918,8 @@ GetMaxResourceConsumerDevice (
/*++
Routine Description:
Get the max resource consumer in the host resource pool
Get the max resource consumer in the host resource pool
Arguments:
@@ -974,7 +978,7 @@ PciHostBridgeAdjustAllocation (
/*++
Routine Description:
Adjust host bridge allocation so as to reduce resource requirement
Arguments:
@@ -1039,7 +1043,7 @@ Returns:
//
return EFI_ABORTED;
}
//
// Hostbridge hasn't enough resource
//
@@ -1047,7 +1051,7 @@ Returns:
if (!PciResNode) {
continue;
}
//
// Check if the device has been removed before
//
@@ -1056,13 +1060,13 @@ Returns:
continue;
}
}
//
// Remove the device if it isn't in the array
//
Status = RejectPciDevice (PciResNode->PciDev);
if (Status == EFI_SUCCESS) {
//
// Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
//
@@ -1399,7 +1403,7 @@ Returns:
// Memory type aperture
//
case 0:
//
// Check to see the granularity
//
@@ -1471,7 +1475,7 @@ Returns:
SubBusNumber = 0;
StartBusNumber = 0;
PciIo = &(BridgeDev->PciIo);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
if (EFI_ERROR (Status)) {
return Status;
@@ -1896,7 +1900,7 @@ Returns:
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
//
// Get Root Brige Handle
//
@@ -1965,7 +1969,7 @@ PciHotPlugRequestNotify (
Routine Description:
Hot plug request notify.
Arguments:
This - A pointer to the hot plug request protocol.
@@ -2082,7 +2086,7 @@ SearchHostBridgeHandle (
/*++
Routine Description:
Arguments:
Returns:
@@ -2130,7 +2134,7 @@ AddHostBridgeEnumerator (
/*++
Routine Description:
Arguments:
Returns:

259
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciEnumeratorSupport.c
Abstract:
PCI Bus Driver
@@ -66,8 +66,9 @@ Returns:
//
// Read the Vendor Id register
//
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
NULL,
EfiPciWidthUint32,
Address,
1,
@@ -80,8 +81,9 @@ Returns:
// Read the entire config header for the device
//
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
NULL,
EfiPciWidthUint32,
Address,
sizeof (PCI_TYPE00) / sizeof (UINT32),
@@ -172,12 +174,12 @@ Returns:
//
PciIo = &(PciIoDevice->PciIo);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Get resource padding for PPB
//
@@ -256,7 +258,7 @@ Returns:
Func
);
if ((PciIoDevice != NULL) && gFullEnumeration) {
InitializeP2C (PciIoDevice);
InitializeP2C (PciIoDevice);
}
} else {
@@ -297,16 +299,18 @@ Returns:
if (!PciIoDevice) {
return EFI_OUT_OF_RESOURCES;
}
//
// Update the bar information for this PCI device so as to support some specific device
//
UpdatePciInfo (PciIoDevice);
if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {
UpdatePciInfo (PciIoDevice);
}
if (PciIoDevice->DevicePath == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// Detect this function has option rom
//
@@ -321,7 +325,7 @@ Returns:
ResetPowerManagementFeature (PciIoDevice);
}
//
// Insert it into a global tree for future reference
//
@@ -452,7 +456,7 @@ Returns:
if (!PciIoDevice) {
return NULL;
}
//
// Create a device path for this PCI device and store it into its private data
//
@@ -486,10 +490,10 @@ Returns:
//
// Test whether it support 32 decode or not
//
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
if (Value) {
if (Value & 0x01) {
@@ -684,20 +688,20 @@ Returns:
// Preserve the original value
//
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
//
// Raise TPL to high level to disable timer interrupt while the BAR is probed
//
OldTpl = gBS->RaiseTPL (EFI_TPL_HIGH_LEVEL);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
//
// Write back the original value
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
//
// Restore TPL to its original level
@@ -771,7 +775,7 @@ Returns:
gBS->RestoreTPL (OldTpl);
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
//
// Preserve the original value
//
@@ -813,7 +817,7 @@ PciSetDeviceAttribute (
/*++
Routine Description:
Set the supported or current attributes of a PCI device
Set the supported or current attributes of a PCI device
Arguments:
PciIoDevice - Structure pointer for PCI device.
@@ -821,7 +825,7 @@ PciSetDeviceAttribute (
BridgeControl - Bridge control value for PPB or P2C.
Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
Returns:
Returns:
--*/
@@ -829,15 +833,15 @@ PciSetDeviceAttribute (
Routine Description:
Arguments:
Returns:
EFI_SUCCESS Always success
--*/
{
@@ -878,7 +882,7 @@ Returns:
if (Option == EFI_SET_SUPPORTS) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |
EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
@@ -929,7 +933,7 @@ GetFastBackToBackSupport (
/*++
Routine Description:
Determine if the device can support Fast Back to Back attribute
Arguments:
@@ -953,11 +957,11 @@ Returns:
// Read the status register
//
PciIo = &PciIoDevice->PciIo;
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
//
// Check the Fast B2B bit
//
@@ -977,7 +981,7 @@ ProcessOptionRomLight (
/*++
Routine Description:
Process the option ROM for all the children of the specified parent PCI device.
It can only be used after the first full Option ROM process.
@@ -1020,7 +1024,7 @@ DetermineDeviceAttribute (
/*++
Routine Description:
Determine the related attributes of all devices under a Root Bridge
Arguments:
@@ -1061,7 +1065,7 @@ Returns:
return Status;
}
} else {
//
// Set the attributes to be checked for common PCI devices and PPB or P2C
// Since some devices only support part of them, it is better to set the
@@ -1100,30 +1104,30 @@ Returns:
/*
if (IS_PCI_IDE(&PciIoDevice->Pci)) {
PciIo = &PciIoDevice->PciIo;
PciIo = &PciIoDevice->PciIo;
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint8,
0x09,
1,
PciIoRead (
PciIo,
EfiPciIoWidthUint8,
0x09,
1,
&IdePI
);
//
// Set native mode if it can be supported
//
//
IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint8,
0x09,
1,
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x09,
1,
&IdePI
);
}
);
}
*/
}
@@ -1135,7 +1139,7 @@ Returns:
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
FastB2BSupport = FALSE;
}
//
// For RootBridge, PPB , P2C, go recursively to traverse all its children
//
@@ -1216,45 +1220,28 @@ Returns:
UINTN BarIndex;
UINTN BarEndIndex;
BOOLEAN SetFlag;
EFI_PCI_DEVICE_INFO PciDeviceInfo;
VOID *Configuration;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
Configuration = NULL;
//
// It can only be supported after the Incompatible PCI Device
// Support Protocol has been installed
//
if (gEfiIncompatiblePciDeviceSupport == NULL) {
Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gEfiIncompatiblePciDeviceSupport
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
}
//
// Check whether the device belongs to incompatible devices or not
// If it is , then get its special requirement in the ACPI table
//
Status = gEfiIncompatiblePciDeviceSupport->CheckDevice (
gEfiIncompatiblePciDeviceSupport,
PciIoDevice->Pci.Hdr.VendorId,
PciIoDevice->Pci.Hdr.DeviceId,
PciIoDevice->Pci.Hdr.RevisionID,
PciIoDevice->Pci.Device.SubsystemVendorID,
PciIoDevice->Pci.Device.SubsystemID,
&Configuration
);
PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;
PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;
PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;
PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;
PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;
Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Update PCI device information from the ACPI table
//
@@ -1289,7 +1276,7 @@ Returns:
SetFlag = FALSE;
switch (Ptr->ResType) {
case ACPI_ADDRESS_SPACE_TYPE_MEM:
//
// Make sure the bar is memory type
//
@@ -1299,7 +1286,7 @@ Returns:
break;
case ACPI_ADDRESS_SPACE_TYPE_IO:
//
// Make sure the bar is IO type
//
@@ -1310,7 +1297,7 @@ Returns:
}
if (SetFlag) {
//
// Update the new alignment for the device
//
@@ -1367,9 +1354,9 @@ Returns:
//
// Check the validity of the parameter
//
if (NewAlignment != PCI_BAR_EVEN_ALIGN &&
if (NewAlignment != PCI_BAR_EVEN_ALIGN &&
NewAlignment != PCI_BAR_SQUAD_ALIGN &&
NewAlignment != PCI_BAR_DQUAD_ALIGN ) {
NewAlignment != PCI_BAR_DQUAD_ALIGN ) {
*Alignment = NewAlignment;
return ;
}
@@ -1384,7 +1371,7 @@ Returns:
OldAlignment = RShiftU64 (OldAlignment, 4);
ShiftBit += 4;
}
//
// Adjust the alignment to even, quad or double quad boundary
//
@@ -1401,7 +1388,7 @@ Returns:
OldAlignment = OldAlignment + 8 - (OldAlignment & 0x07);
}
}
//
// Update the old value
//
@@ -1563,7 +1550,7 @@ Returns:
for (Data = Value; Data != 0; Data >>= 1) {
Index ++;
}
Value |= ((UINT32)(-1) << Index);
Value |= ((UINT32)(-1) << Index);
//
// Calculate the size of 64bit bar
@@ -1587,7 +1574,7 @@ Returns:
break;
}
}
//
// Check the length again so as to keep compatible with some special bars
//
@@ -1596,7 +1583,7 @@ Returns:
PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
PciIoDevice->PciBar[BarIndex].Alignment = 0;
}
//
// Increment number of bar
//
@@ -1610,7 +1597,7 @@ InitializePciDevice (
/*++
Routine Description:
This routine is used to initialize the bar of a PCI device
It can be called typically when a device is going to be rejected
@@ -1635,7 +1622,7 @@ Returns:
// has not been alloacted
//
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
}
return EFI_SUCCESS;
@@ -1668,28 +1655,28 @@ Returns:
// Io32, pMem32, pMem64 to quiescent state
// Resource base all ones, Resource limit all zeros
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
//
// don't support use io32 as for now
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
//
// Force Interrupt line to zero for cards that come up randomly
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
return EFI_SUCCESS;
}
@@ -1721,22 +1708,22 @@ Returns:
// Io32, pMem32, pMem64 to quiescent state(
// Resource base all ones, Resource limit all zeros
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
//
// Force Interrupt line to zero for cards that come up randomly
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
return EFI_SUCCESS;
}
@@ -1845,7 +1832,7 @@ PciEnumeratorLight (
Routine Description:
This routine is used to enumerate entire pci bus system
This routine is used to enumerate entire pci bus system
in a given platform
Arguments:
@@ -1910,7 +1897,7 @@ Returns:
Descriptors++;
continue;
}
//
// Record the root bridge io protocol
//
@@ -1922,7 +1909,7 @@ Returns:
);
if (!EFI_ERROR (Status)) {
//
// Remove those PCI devices which are rejected when full enumeration
//
@@ -1975,9 +1962,9 @@ Arguments:
MinBus - The min bus.
MaxBus - The max bus.
BusRange - The bus range.
Returns:
Status Code.
--*/
@@ -2129,11 +2116,11 @@ Returns:
}
if (TestValue & 0x01) {
//
// IO Bar
//
Mask = 0xFFFFFFFC;
TestValue = TestValue & Mask;
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
@@ -2141,26 +2128,26 @@ Returns:
}
} else {
//
// Mem Bar
//
Mask = 0xFFFFFFF0;
TestValue = TestValue & Mask;
if ((TestValue & 0x07) == 0x04) {
//
// Mem64 or PMem64
//
BarOffset += sizeof (UINT32);
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
//
// Test its high 32-Bit BAR
//
Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
if (TestValue == OldValue) {
return TRUE;
@@ -2168,7 +2155,7 @@ Returns:
}
} else {
//
// Mem32 or PMem32
//
@@ -2207,7 +2194,7 @@ Returns:
EFI_STATUS Status;
PCI_TYPE00 Pci;
UINT8 Device;
UINT32 Register;
UINT32 Register;
UINT8 Func;
UINT64 Address;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
@@ -2231,9 +2218,10 @@ Returns:
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {
Register = 0;
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
EfiPciWidthUint32,
&Pci,
EfiPciWidthUint32,
Address,
1,
&Register
@@ -2242,9 +2230,10 @@ Returns:
// Reset register 18h, 19h, 1Ah on PCI Bridge
//
Register &= 0xFF000000;
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
EfiPciWidthUint32,
&Pci,
EfiPciWidthUint32,
Address,
1,
&Register

1009
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.c
View File

File diff suppressed because it is too large Load Diff

126
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciLib.h
Abstract:
PCI Bus Driver Lib header file.
@@ -26,6 +26,15 @@ Revision History
#ifndef _EFI_PCI_LIB_H
#define _EFI_PCI_LIB_H
//
// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
//
#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01
#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02
#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04
#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08
#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a
VOID
InstallHotPlugRequestProtocol (
IN EFI_STATUS *Status
@@ -274,4 +283,103 @@ Returns:
--*/
;
/**
Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciIoRead (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciIoWrite (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciRootBridgeIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciRootBridgeIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
#endif

32
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciOptionRomSupport.c
Abstract:
PCI Bus Driver
@@ -88,8 +88,9 @@ Returns:
AllOnes = 0xfffffffe;
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32,
Address,
1,
@@ -98,12 +99,13 @@ Returns:
if (EFI_ERROR (Status)) {
return Status;
}
//
// read back
//
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32,
Address,
1,
@@ -334,7 +336,7 @@ Returns:
// Clear all bars
//
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
}
//
@@ -342,7 +344,7 @@ Returns:
// enable its decoder
//
Value32 = RomBar | 0x1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,
@@ -376,7 +378,7 @@ Returns:
// disable rom decode
//
Value32 = 0xFFFFFFFE;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,

32
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciPowerManagement.c
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciPowerManagement.c
Abstract:
PCI Bus Driver
@@ -71,13 +71,13 @@ Returns:
//
// Write PMCSR
//
PciIoDevice->PciIo.Pci.Write (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
PowerManagementRegBlock + 4,
1,
&PMCSR
);
PciIoWrite (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
PowerManagementRegBlock + 4,
1,
&PMCSR
);
return EFI_SUCCESS;
}

80
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciResourceSupport.c
Abstract:
PCI Bus Driver
@@ -1222,7 +1222,7 @@ Returns:
case PciBarTypeMem32:
case PciBarTypePMem32:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@@ -1239,7 +1239,7 @@ Returns:
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@@ -1249,7 +1249,7 @@ Returns:
Address32 = (UINT32) RShiftU64 (Address, 32);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
@@ -1317,7 +1317,7 @@ Returns:
case PPB_BAR_0:
case PPB_BAR_1:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@@ -1333,7 +1333,7 @@ Returns:
case PPB_IO_RANGE:
Address32 = ((UINT32) (Address)) >> 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x1C,
@@ -1342,7 +1342,7 @@ Returns:
);
Address32 >>= 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x30,
@@ -1352,7 +1352,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x1D,
@@ -1361,7 +1361,7 @@ Returns:
);
Address32 >>= 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x32,
@@ -1376,7 +1376,7 @@ Returns:
case PPB_MEM32_RANGE:
Address32 = ((UINT32) (Address)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x20,
@@ -1386,7 +1386,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x22,
@@ -1402,7 +1402,7 @@ Returns:
case PPB_PMEM64_RANGE:
Address32 = ((UINT32) (Address)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x24,
@@ -1412,7 +1412,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x26,
@@ -1421,7 +1421,7 @@ Returns:
);
Address32 = (UINT32) RShiftU64 (Address, 32);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x28,
@@ -1430,7 +1430,7 @@ Returns:
);
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x2C,
@@ -1915,7 +1915,7 @@ Returns:
switch (Node->Bar) {
case P2C_BAR_0:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@@ -1928,7 +1928,7 @@ Returns:
break;
case P2C_MEM_1:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x1c,
@@ -1937,7 +1937,7 @@ Returns:
);
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x20,
@@ -1950,7 +1950,7 @@ Returns:
//
// Set non-prefetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -1959,7 +1959,7 @@ Returns:
);
BridgeControl &= 0xfeff;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -1972,7 +1972,7 @@ Returns:
//
// Set pre-fetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -1981,7 +1981,7 @@ Returns:
);
BridgeControl |= 0x0100;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -1997,7 +1997,7 @@ Returns:
break;
case P2C_MEM_2:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x24,
@@ -2007,7 +2007,7 @@ Returns:
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x28,
@@ -2020,7 +2020,7 @@ Returns:
//
// Set non-prefetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -2029,7 +2029,7 @@ Returns:
);
BridgeControl &= 0xfdff;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -2041,7 +2041,7 @@ Returns:
//
// Set pre-fetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -2050,7 +2050,7 @@ Returns:
);
BridgeControl |= 0x0200;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@@ -2065,7 +2065,7 @@ Returns:
break;
case P2C_IO_1:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x2c,
@@ -2073,7 +2073,7 @@ Returns:
&Address
);
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x30,
@@ -2088,7 +2088,7 @@ Returns:
break;
case P2C_IO_2:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x34,
@@ -2097,7 +2097,7 @@ Returns:
);
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x38,

45
EdkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.c
View File

@@ -1,24 +1,24 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciBus.c
Abstract:
PCI Bus Driver
Revision History
--*/
#include "pcibus.h"
@@ -36,7 +36,6 @@ EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
NULL
};
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport = NULL;
EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
UINTN gPciHostBridgeNumber;
BOOLEAN gFullEnumeration;
@@ -68,8 +67,8 @@ Arguments:
Returns:
EFI_SUCCESS
EFI_DEVICE_ERROR
EFI_SUCCESS
EFI_DEVICE_ERROR
--*/
// TODO: ImageHandle - add argument and description to function comment
@@ -101,7 +100,7 @@ Routine Description:
Check to see if pci bus driver supports the given controller
Arguments:
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
@@ -195,13 +194,13 @@ Routine Description:
Start to management the controller passed in
Arguments:
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
Returns:
--*/
// TODO: This - add argument and description to function comment
@@ -211,12 +210,6 @@ Returns:
{
EFI_STATUS Status;
Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gEfiIncompatiblePciDeviceSupport
);
//
// If PCI Platform protocol is available, get it now.
// If the platform implements this, it must be installed before BDS phase
@@ -240,12 +233,12 @@ Returns:
if (EFI_ERROR (Status)) {
return Status;
}
//
// Enable PCI device specified by remaining device path. BDS or other driver can call the
// start more than once.
//
StartPciDevices (Controller, RemainingDevicePath);
return EFI_SUCCESS;
@@ -267,7 +260,7 @@ Routine Description:
if all the the children get closed, close the protocol
Arguments:
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
@@ -275,7 +268,7 @@ Arguments:
Returns:
--*/
// TODO: This - add argument and description to function comment
// TODO: Controller - add argument and description to function comment

19
EdkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.h
View File

@@ -1,18 +1,18 @@
/*++
Copyright (c) 2006, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
pcibus.h
Abstract:
PCI Bus Driver
@@ -216,7 +216,6 @@ typedef struct _PCI_IO_DEVICE {
//
// Global Variables
//
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
extern LIST_ENTRY gPciDevicePool;