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Add generic HPET Timer DXE Driver and support libraries

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Signed-off-by: mdkinney
Reviewed-by: li-elvin

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12260 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
mdkinney
2011-09-02 02:43:51 +00:00
parent 5f867ad00d
commit 986d1dfb08
9 changed files with 1441 additions and 0 deletions
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102
PcAtChipsetPkg/Include/Library/IoApicLib.h Normal file
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/** @file
Public include file for I/O APIC library.
I/O APIC library assumes I/O APIC is enabled. It does not
handles cases where I/O APIC is disabled.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Read a 32-bit I/O APIC register.
If Index is >= 0x100, then ASSERT().
@param Index Specifies the I/O APIC register to read.
@return The 32-bit value read from the I/O APIC register specified by Index.
**/
UINT32
EFIAPI
IoApicRead (
IN UINTN Index
);
/**
Write a 32-bit I/O APIC register.
If Index is >= 0x100, then ASSERT().
@param Index Specifies the I/O APIC register to write.
@param Value Specifies the value to write to the I/O APIC register specified by Index.
@return The 32-bit value written to I/O APIC register specified by Index.
**/
UINT32
EFIAPI
IoApicWrite (
IN UINTN Index,
IN UINT32 Value
);
/**
Set the interrupt mask of an I/O APIC interrupt.
If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
@param Irq Specifies the I/O APIC interrupt to enable or disable.
@param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
If FALSE, then disable the I/O APIC interrupt specified by Irq.
**/
VOID
EFIAPI
IoApicEnableInterrupt (
IN UINTN Irq,
IN BOOLEAN Enable
);
/**
Configures an I/O APIC interrupt.
Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
mode to the Local APIC of the currntly executing CPU. The default state of the
entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
be used to enable(unmask) the I/O APIC Interrupt.
If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
If Vector >= 0x100, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Irq Specifies the I/O APIC interrupt to initialize.
@param Vector The 8-bit interrupt vector associated with the I/O APIC
Interrupt. Must be in the range 0x10..0xFE.
@param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
interrupt is handled. The only supported values are:
0: IO_APIC_DELIVERY_MODE_FIXED
1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
2: IO_APIC_DELIVERY_MODE_SMI
4: IO_APIC_DELIVERY_MODE_NMI
5: IO_APIC_DELIVERY_MODE_INIT
7: IO_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel TRUE specified an active high interrupt.
FALSE specifies an active low interrupt.
**/
VOID
EFIAPI
IoApicConfigureInterrupt (
IN UINTN Irq,
IN UINTN Vector,
IN UINTN DeliveryMode,
IN BOOLEAN LevelTriggered,
IN BOOLEAN AssertionLevel
);

106
PcAtChipsetPkg/Include/Register/Hpet.h Normal file
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/** @file
HPET register definitions from the IA-PC HPET (High Precision Event Timers)
Specification, Revision 1.0a, October 2004.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __HPET_REGISTER_H__
#define __HPET_REGISTER_H__
///
/// HPET General Register Offsets
///
#define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000
#define HPET_GENERAL_CONFIGURATION_OFFSET 0x010
#define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020
///
/// HPET Timer Register Offsets
///
#define HPET_MAIN_COUNTER_OFFSET 0x0F0
#define HPET_TIMER_CONFIGURATION_OFFSET 0x100
#define HPET_TIMER_COMPARATOR_OFFSET 0x108
#define HPET_TIMER_MSI_ROUTE_OFFSET 0x110
///
/// Stride between sets of HPET Timer Registers
///
#define HPET_TIMER_STRIDE 0x20
#pragma pack(1)
///
/// HPET General Capabilities and ID Register
///
typedef union {
struct {
UINT32 Revision:8;
UINT32 NumberOfTimers:5;
UINT32 CounterSize:1;
UINT32 Reserved0:1;
UINT32 LegacyRoute:1;
UINT32 VendorId:16;
UINT32 CounterClockPeriod:32;
} Bits;
UINT64 Uint64;
} HPET_GENERAL_CAPABILITIES_ID_REGISTER;
///
/// HPET General Configuration Register
///
typedef union {
struct {
UINT32 MainCounterEnable:1;
UINT32 LegacyRouteEnable:1;
UINT32 Reserved0:30;
UINT32 Reserved1:32;
} Bits;
UINT64 Uint64;
} HPET_GENERAL_CONFIGURATION_REGISTER;
///
/// HPET Timer Configuration Register
///
typedef union {
struct {
UINT32 Reserved0:1;
UINT32 LevelTriggeredInterrupt:1;
UINT32 InterruptEnable:1;
UINT32 PeriodicInterruptEnable:1;
UINT32 PeriodicInterruptCapablity:1;
UINT32 CounterSizeCapablity:1;
UINT32 ValueSetEnable:1;
UINT32 Reserved1:1;
UINT32 CounterSizeEnable:1;
UINT32 InterruptRoute:5;
UINT32 MsiInterruptEnable:1;
UINT32 MsiInterruptCapablity:1;
UINT32 Reserved2:16;
UINT32 InterruptRouteCapability;
} Bits;
UINT64 Uint64;
} HPET_TIMER_CONFIGURATION_REGISTER;
///
/// HPET Timer MSI Route Register
///
typedef union {
struct {
UINT32 Value:32;
UINT32 Address:32;
} Bits;
UINT64 Uint64;
} HPET_TIMER_MSI_ROUTE_REGISTER;
#pragma pack()
#endif

86
PcAtChipsetPkg/Include/Register/IoApic.h Normal file
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/** @file
I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt
Controller (IOAPIC), 1996.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __IO_APIC_H__
#define __IO_APIC_H__
///
/// I/O APIC Register Offsets
///
#define IOAPIC_INDEX_OFFSET 0x00
#define IOAPIC_DATA_OFFSET 0x10
///
/// I/O APIC Indirect Register Indexes
///
#define IO_APIC_IDENTIFICATION_REGISTER_INDEX 0x00
#define IO_APIC_VERSION_REGISTER_INDEX 0x01
#define IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX 0x10
///
/// I/O APIC Interrupt Deliver Modes
///
#define IO_APIC_DELIVERY_MODE_FIXED 0
#define IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
#define IO_APIC_DELIVERY_MODE_SMI 2
#define IO_APIC_DELIVERY_MODE_NMI 4
#define IO_APIC_DELIVERY_MODE_INIT 5
#define IO_APIC_DELIVERY_MODE_EXTINT 7
#pragma pack(1)
typedef union {
struct {
UINT32 Reserved0:24;
UINT32 Identification:4;
UINT32 Reserved1:4;
} Bits;
UINT32 Uint32;
} IO_APIC_IDENTIFICATION_REGISTER;
typedef union {
struct {
UINT32 Version:8;
UINT32 Reserved0:8;
UINT32 MaximumRedirectionEntry:8;
UINT32 Reserved1:8;
} Bits;
UINT32 Uint32;
} IO_APIC_VERSION_REGISTER;
typedef union {
struct {
UINT32 Vector: 8;
UINT32 DeliveryMode: 3;
UINT32 DestinationMode: 1;
UINT32 DeliveryStatus: 1;
UINT32 Polarity: 1;
UINT32 RemoteIRR: 1;
UINT32 TriggerMode: 1;
UINT32 Mask: 1;
UINT32 Reserved0: 15;
UINT32 Reserved1: 24;
UINT32 DestinationID: 8;
} Bits;
struct {
UINT32 Low;
UINT32 High;
} Uint32;
UINT64 Uint64;
} IO_APIC_REDIRECTION_TABLE_ENTRY;
#pragma pack()
#endif