Introduce UefiCpuLib library class in UefiCpuPkg and add one instance of BaseUefiCpuLib. The major purpose of this library class / instance is to provide some routines that are generic for IA32 family CPU

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9480 6f19259b-4bc3-4df7-8a09-765794883524

UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S

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+#------------------------------------------------------------------------------
+#*
+#*   Copyright 2009, Intel Corporation
+#*   All rights reserved. This program and the accompanying materials
+#*   are licensed and made available under the terms and conditions of the BSD License
+#*   which accompanies this distribution.  The full text of the license may be found at
+#*   http://opensource.org/licenses/bsd-license.php
+#*
+#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*
+#------------------------------------------------------------------------------
+
+
+
+#
+# Float control word initial value: 
+# all exceptions masked, double-precision, round-to-nearest
+#
+ASM_PFX(mFpuControlWord): .word     0x027F
+#
+# Multimedia-extensions control word:
+# all exceptions masked, round-to-nearest, flush to zero for masked underflow
+#
+ASM_PFX(mMmxControlWord): .long     0x01F80
+
+#
+# Initializes floating point units for requirement of UEFI specification.
+#
+# This function initializes floating-point control word to 0x027F (all exceptions
+# masked,double-precision, round-to-nearest) and multimedia-extensions control word
+# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
+# for masked underflow).
+#
+ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
+ASM_PFX(InitializeFloatingPointUnits):
+    #
+    # Initialize floating point units
+    #
+    finit
+    fldcw   ASM_PFX(mFpuControlWord)
+    
+    #
+    # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+    # whether the processor supports SSE instruction.
+    #
+    movl    $1,  %eax
+    cpuid
+    btl     $25, %edx
+    jnc     Done
+    
+    #
+    # Set OSFXSR bit 9 in CR4
+    #
+    movl    %cr4, %eax 
+    or      $200, %eax
+    movl    %eax, %cr4
+    
+    #
+    # The processor should support SSE instruction and we can use
+    # ldmxcsr instruction
+    #
+    ldmxcsr ASM_PFX(mMmxControlWord)
+
+Done:
+    ret
+
+#END
+