Sync gcc with armasm. update some memory barriers.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10025 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -24,95 +24,55 @@
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EXPORT ArmSetDomainAccessControl
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EXPORT CPSRMaskInsert
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EXPORT CPSRRead
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EXPORT ReadCCSIDR
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AREA ArmLibSupport, CODE, READONLY
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Cp15IdCode
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DSB
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ISB
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mrc p15,0,R0,c0,c0,0
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DSB
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ISB
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bx LR
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Cp15CacheInfo
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DSB
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ISB
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mrc p15,0,R0,c0,c0,1
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DSB
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ISB
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bx LR
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ArmEnableInterrupts
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DSB
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ISB
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mrs R0,CPSR
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bic R0,R0,#0x80 ;Enable IRQ interrupts
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msr CPSR_c,R0
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DSB
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ISB
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CPSIE i
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bx LR
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ArmDisableInterrupts
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DSB
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ISB
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mrs R0,CPSR
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orr R1,R0,#0x80 ;Disable IRQ interrupts
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msr CPSR_c,R1
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tst R0,#0x80
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moveq R0,#1
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movne R0,#0
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DSB
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ISB
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CPSID i
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bx LR
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ArmGetInterruptState
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DSB
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ISB
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mrs R0,CPSR
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tst R0,#0x80 ;Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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DSB
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ISB
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bx LR
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ArmInvalidateTlb
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DSB
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ISB
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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DSB
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ISB
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bx lr
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ArmSetTranslationTableBaseAddress
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DSB
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ISB
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mcr p15,0,r0,c2,c0,0
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DSB
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ISB
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bx lr
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ArmGetTranslationTableBaseAddress
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DSB
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ISB
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mrc p15,0,r0,c2,c0,0
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DSB
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ISB
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bx lr
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ArmSetDomainAccessControl
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DSB
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ISB
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mcr p15,0,r0,c3,c0,0
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DSB
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ISB
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bx lr
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CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
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DSB
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ISB
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stmfd sp!, {r4-r12, lr} ; save all the banked registers
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mov r3, sp ; copy the stack pointer into a non-banked register
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mrs r2, cpsr ; read the cpsr
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@@ -120,20 +80,33 @@ CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to in
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and r1, r1, r0 ; clear bits outside the mask in the input
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orr r2, r2, r1 ; set field
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msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
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ISB
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mov sp, r3 ; restore stack pointer
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ldmfd sp!, {r4-r12, lr} ; restore registers
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DSB
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ISB
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bx lr ; return (hopefully thumb-safe!)
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CPSRRead
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DSB
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ISB
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mrs r0, cpsr
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DSB
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ISB
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bx lr
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// UINT32
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// ReadCCSIDR (
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// IN UINT32 CSSELR
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// )
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ReadCCSIDR
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MCR p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
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ISB
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MRC p15,1,<Rt>,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
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BX lr
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// UINT32
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// ReadCLIDR (
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// IN UINT32 CSSELR
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// )
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ReadCLIDR
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MRC p15,1,<Rt>,c0,c0,1 ; Read CP15 Cache Level ID Register
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END
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