Sync gcc with armasm. update some memory barriers.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10025 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2010-02-19 18:51:10 +00:00
parent 752d258a42
commit 98bc0c8c05
10 changed files with 570 additions and 153 deletions

View File

@@ -24,95 +24,55 @@
EXPORT ArmSetDomainAccessControl
EXPORT CPSRMaskInsert
EXPORT CPSRRead
EXPORT ReadCCSIDR
AREA ArmLibSupport, CODE, READONLY
Cp15IdCode
DSB
ISB
mrc p15,0,R0,c0,c0,0
DSB
ISB
bx LR
Cp15CacheInfo
DSB
ISB
mrc p15,0,R0,c0,c0,1
DSB
ISB
bx LR
ArmEnableInterrupts
DSB
ISB
mrs R0,CPSR
bic R0,R0,#0x80 ;Enable IRQ interrupts
msr CPSR_c,R0
DSB
ISB
CPSIE i
bx LR
ArmDisableInterrupts
DSB
ISB
mrs R0,CPSR
orr R1,R0,#0x80 ;Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
DSB
ISB
CPSID i
bx LR
ArmGetInterruptState
DSB
ISB
mrs R0,CPSR
tst R0,#0x80 ;Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
DSB
ISB
bx LR
ArmInvalidateTlb
DSB
ISB
mov r0,#0
mcr p15,0,r0,c8,c7,0
DSB
ISB
bx lr
ArmSetTranslationTableBaseAddress
DSB
ISB
mcr p15,0,r0,c2,c0,0
DSB
ISB
bx lr
ArmGetTranslationTableBaseAddress
DSB
ISB
mrc p15,0,r0,c2,c0,0
DSB
ISB
bx lr
ArmSetDomainAccessControl
DSB
ISB
mcr p15,0,r0,c3,c0,0
DSB
ISB
bx lr
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
DSB
ISB
stmfd sp!, {r4-r12, lr} ; save all the banked registers
mov r3, sp ; copy the stack pointer into a non-banked register
mrs r2, cpsr ; read the cpsr
@@ -120,20 +80,33 @@ CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to in
and r1, r1, r0 ; clear bits outside the mask in the input
orr r2, r2, r1 ; set field
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
ISB
mov sp, r3 ; restore stack pointer
ldmfd sp!, {r4-r12, lr} ; restore registers
DSB
ISB
bx lr ; return (hopefully thumb-safe!)
CPSRRead
DSB
ISB
mrs r0, cpsr
DSB
ISB
bx lr
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ReadCCSIDR
MCR p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
ISB
MRC p15,1,<Rt>,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
BX lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ReadCLIDR
MRC p15,1,<Rt>,c0,c0,1 ; Read CP15 Cache Level ID Register
END