QuarkSocPkg: Add new package for Quark SoC X1000
Changes for V4 ============== 1) Remove Unicode character from C source file 2) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode from QuarkPlatformPkg commit to QuarkSocPkg commit Changes for V2 ============== 1) Sync with new APIs in SmmCpuFeaturesLib class 2) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg 3) Remove PCI serial driver from QuarkSocPkg 4) Apply optimizations to MtrrLib from MtrrLib in UefiCpuPkg 5) Convert all UNI files to utf-8 6) Replace tabs with spaces and remove trailing spaces 7) Add License.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19286 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
mdkinney
257
QuarkSocPkg/QuarkNorthCluster/Include/DdrMemoryController.h
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257
QuarkSocPkg/QuarkNorthCluster/Include/DdrMemoryController.h
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@@ -0,0 +1,257 @@
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/** @file
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Memory controller configuration.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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||||
|
||||
**/
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#ifndef __DDR_MEMORY_CONTROLLER_H__
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#define __DDR_MEMORY_CONTROLLER_H__
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//
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// DDR timing data definitions.
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// These are used to create bitmaps of valid timing configurations.
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//
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#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN 0xFF
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#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05 0x05
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06 0x04
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL 0x07
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#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED 0x01
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#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED 0x02
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#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED 0x04
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#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED 0x08
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#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR 0x10
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#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR 0x20
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//
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// Maximum number of SDRAM channels supported by the memory controller
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//
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#define MAX_CHANNELS 1
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//
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// Maximum number of DIMM sockets supported by the memory controller
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//
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#define MAX_SOCKETS 1
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//
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// Maximum number of sides supported per DIMM
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//
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#define MAX_SIDES 2
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//
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// Maximum number of "Socket Sets", where a "Socket Set is a set of matching
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// DIMM's from the various channels
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//
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#define MAX_SOCKET_SETS 2
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//
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// Maximum number of rows supported by the memory controller
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//
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#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
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//
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// Maximum number of memory ranges supported by the memory controller
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//
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#define MAX_RANGES (MAX_ROWS + 5)
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//
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// Maximum Number of Log entries
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//
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#define MEMORY_LOG_MAX_INDEX 16
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typedef struct _MEMORY_LOG_ENTRY {
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EFI_STATUS_CODE_VALUE Event;
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EFI_STATUS_CODE_TYPE Severity;
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UINT8 Data;
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} MEMORY_LOG_ENTRY;
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typedef struct _MEMORY_LOG {
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UINT8 Index;
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MEMORY_LOG_ENTRY Entry[MEMORY_LOG_MAX_INDEX];
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} MEMORY_LOG;
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//
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// Defined ECC types
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//
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#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE 0x01 // No error checking
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#define DUAL_CHANNEL_DDR_ECC_TYPE_EC 0x02 // Error checking only
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#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC 0x04 // Software Scrubbing ECC
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#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC 0x08 // Hardware Scrubbing ECC
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#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC 0x10 // Chip Kill ECC
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//
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// Row configuration status values
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//
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS 0x00 // No error
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN 0x01 // Pattern mismatch, no memory
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED 0x02 // Memory type not supported
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR 0x03 // Row/Col/Bnk mismatch
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR 0x04 // Received ECC error
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT 0x05 // Row is not present
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED 0x06 // Row is disabled
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//
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// Memory range types
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//
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typedef enum {
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DualChannelDdrMainMemory,
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DualChannelDdrSmramCacheable,
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DualChannelDdrSmramNonCacheable,
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DualChannelDdrGraphicsMemoryCacheable,
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DualChannelDdrGraphicsMemoryNonCacheable,
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DualChannelDdrReservedMemory,
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DualChannelDdrMaxMemoryRangeType
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} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
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//
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// Memory map range information
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//
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typedef struct {
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EFI_PHYSICAL_ADDRESS PhysicalAddress;
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EFI_PHYSICAL_ADDRESS CpuAddress;
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EFI_PHYSICAL_ADDRESS RangeLength;
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DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;
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} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
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typedef struct {
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unsigned dramType :1; /**< Type: 0 = RESERVED; 1 = DDR2 */
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unsigned dramWidth :1; /**< Width: 0 = x8; 1 = x16 */
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unsigned dramDensity :2; /**< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb */
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unsigned dramSpeed :1; /**< Speed Grade: 0 = RESERVED; 1 = 800MT/s;*/
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unsigned dramTimings :3; /**< Timings: 4-4-4, 5-5-5, 6-6-6 */
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unsigned dramRanks :1; /**< Ranks: 0 = Single Rank; 1 = Dual Rank */
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} DramGeometry; /**< DRAM Geometry Descriptor */
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typedef union _RegDRP {
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UINT32 raw;
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struct {
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unsigned rank0Enabled :1; /**< Rank 0 Enable */
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unsigned rank0DevWidth :2; /**< DRAM Device Width (x8,x16) */
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unsigned rank0DevDensity :2; /**< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) */
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unsigned reserved2 :1;
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unsigned rank1Enabled :1; /**< Rank 1 Enable */
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unsigned reserved3 :5;
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unsigned dramType :1; /**< DRAM Type (0=DDR2) */
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unsigned reserved4 :5;
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unsigned reserved5 :14;
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} field;
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} RegDRP; /**< DRAM Rank Population and Interface Register */
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typedef union {
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UINT32 raw;
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struct {
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unsigned dramFrequency :3; /**< DRAM Frequency (000=RESERVED,010=667,011=800) */
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unsigned tRP :2; /**< Precharge to Activate Delay (3,4,5,6) */
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unsigned reserved1 :1;
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unsigned tRCD :2; /**< Activate to CAS Delay (3,4,5,6) */
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unsigned reserved2 :1;
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unsigned tCL :2; /**< CAS Latency (3,4,5,6) */
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unsigned reserved3 :21;
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} field;
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} RegDTR0; /**< DRAM Timing Register 0 */
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typedef union {
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UINT32 raw;
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struct {
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unsigned tWRRD_dly :2; /**< Additional Write to Read Delay (0,1,2,3) */
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unsigned reserved1 :1;
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unsigned tRDWR_dly :2; /**< Additional Read to Write Delay (0,1,2,3) */
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unsigned reserved2 :1;
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unsigned tRDRD_dr_dly :1; /**< Additional Read to Read Delay (1,2) */
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unsigned reserved3 :1;
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unsigned tRD_dly :3; /**< Additional Read Data Sampling Delay (0-7) */
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unsigned reserved4 :1;
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unsigned tRCVEN_halfclk_dly :4; /**< Additional RCVEN Half Clock Delay Control */
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unsigned reserved5 :1;
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unsigned readDqDelay :2; /**< Read DQ Delay */
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unsigned reserved6 :13;
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} field;
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} RegDTR1; /**< DRAM Timing Register 1 */
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typedef union {
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UINT32 raw;
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struct {
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unsigned ckStaticDisable :1; /**< CK/CK# Static Disable */
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unsigned reserved1 :3;
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unsigned ckeStaticDisable :2; /**< CKE Static Disable */
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unsigned reserved2 :8;
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unsigned refreshPeriod :2; /**< Refresh Period (disabled,128clks,3.9us,7.8us) */
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unsigned refreshQueueDepth :2; /**< Refresh Queue Depth (1,2,4,8) */
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unsigned reserved5 :13;
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unsigned initComplete :1; /**< Initialization Complete */
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} field;
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} RegDCO;
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//
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// MRC Data Structure
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//
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typedef struct {
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RegDRP drp;
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RegDTR0 dtr0;
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RegDTR1 dtr1;
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RegDCO dco;
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UINT32 reg0104;
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UINT32 reg0120;
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UINT32 reg0121;
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UINT32 reg0123;
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UINT32 reg0111;
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UINT32 reg0130;
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UINT8 refreshPeriod; /**< Placeholder for the chosen refresh
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* period. This value will NOT be
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* programmed into DCO until all
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* initialization is done.
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*/
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UINT8 ddr2Odt; /**< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm */
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UINT8 sku; /**< Detected QuarkNcSocId SKU */
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UINT8 capabilities; /**< Capabilities Available on this part */
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UINT8 state; /**< NORMAL_BOOT, S3_RESUME */
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UINT32 memSize; /**< Memory size */
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UINT16 pmBase; /**< PM Base */
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UINT16 mrcVersion; /**< MRC Version */
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UINT32 hecbase; /**< HECBASE shifted left 16 bits */
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DramGeometry geometry; /**< DRAM Geometry */
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} MRC_DATA_STRUCTURE; /**< QuarkNcSocId Memory Parameters for MRC */
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typedef struct _EFI_MEMINIT_CONFIG_DATA {
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MRC_DATA_STRUCTURE MrcData;
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} EFI_MEMINIT_CONFIG_DATA;
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|
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#endif
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23
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCBase.h
Normal file
23
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCBase.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/** @file
|
||||
Public include file for the QNC Base
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
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|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __INTEL_QNC_BASE_H__
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||||
#define __INTEL_QNC_BASE_H__
|
||||
|
||||
#include <IntelQNCRegs.h>
|
||||
#include <IntelQNCConfig.h>
|
||||
|
||||
#endif
|
||||
|
||||
106
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCConfig.h
Normal file
106
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCConfig.h
Normal file
@@ -0,0 +1,106 @@
|
||||
/** @file
|
||||
Some configuration of QNC Package
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __INTEL_QNC_CONFIG_H__
|
||||
#define __INTEL_QNC_CONFIG_H__
|
||||
|
||||
//
|
||||
// QNC Fixed configurations.
|
||||
//
|
||||
|
||||
//
|
||||
// Memory arbiter fixed config values.
|
||||
//
|
||||
#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\
|
||||
(ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \
|
||||
(ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \
|
||||
(ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \
|
||||
(ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \
|
||||
))
|
||||
|
||||
//
|
||||
// Memory Manager fixed config values.
|
||||
//
|
||||
#define V_DRAM_NON_HOST_RQ_LIMIT 2
|
||||
|
||||
//
|
||||
// RMU Thermal config fixed config values for TS in Vref Mode.
|
||||
//
|
||||
#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04
|
||||
#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01
|
||||
#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1
|
||||
#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b
|
||||
#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34
|
||||
|
||||
//
|
||||
// RMU Thermal config fixed config values for TS in Ratiometric mode.
|
||||
//
|
||||
#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04
|
||||
#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02
|
||||
#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1
|
||||
#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f
|
||||
#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001
|
||||
#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01
|
||||
#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00
|
||||
#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0
|
||||
#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0
|
||||
#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8
|
||||
#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17
|
||||
|
||||
//
|
||||
// iCLK fixed config values.
|
||||
//
|
||||
#define V_MUXTOP_FLEX2 3
|
||||
#define V_MUXTOP_FLEX1 1
|
||||
|
||||
//
|
||||
// PCIe Root Port fixed config values.
|
||||
//
|
||||
#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)
|
||||
|
||||
//
|
||||
// QNC structures for configuration.
|
||||
//
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
UINT32 PortErrorMask :8;
|
||||
UINT32 SlotImplemented :1;
|
||||
UINT32 Reserved1 :1;
|
||||
UINT32 AspmEnable :1;
|
||||
UINT32 AspmAutoEnable :1;
|
||||
UINT32 AspmL0sEnable :2;
|
||||
UINT32 AspmL1Enable :1;
|
||||
UINT32 PmeInterruptEnable :1;
|
||||
UINT32 PhysicalSlotNumber :13;
|
||||
UINT32 Reserved2 :1;
|
||||
UINT32 PmSciEnable :1;
|
||||
UINT32 HotplugSciEnable :1;
|
||||
} Bits;
|
||||
UINT32 Uint32;
|
||||
} PCIEXP_ROOT_PORT_CONFIGURATION;
|
||||
|
||||
typedef union {
|
||||
UINT32 Uint32;
|
||||
struct {
|
||||
UINT32 Pcie_0 :1; // 0: Disabled; 1: Enabled*
|
||||
UINT32 Pcie_1 :1; // 0: Disabled; 1: Enabled*
|
||||
UINT32 Smbus :1; // 0: Disabled; 1: Enabled*
|
||||
UINT32 Rsvd :29; // 0
|
||||
} Bits;
|
||||
} QNC_DEVICE_ENABLES;
|
||||
|
||||
#endif
|
||||
|
||||
23
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCDxe.h
Normal file
23
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCDxe.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/** @file
|
||||
Public include file for the QNC Dxe
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __INTEL_QNC_DXE_H__
|
||||
#define __INTEL_QNC_DXE_H__
|
||||
|
||||
#include <IntelQNCRegs.h>
|
||||
#include <IntelQNCConfig.h>
|
||||
|
||||
#endif
|
||||
|
||||
23
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCPeim.h
Normal file
23
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCPeim.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/** @file
|
||||
Public include file for the QNC Pei
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __INTEL_QNC_PEIM_H__
|
||||
#define __INTEL_QNC_PEIM_H__
|
||||
|
||||
#include <IntelQNCRegs.h>
|
||||
#include <IntelQNCConfig.h>
|
||||
|
||||
#endif
|
||||
|
||||
54
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCRegs.h
Normal file
54
QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCRegs.h
Normal file
@@ -0,0 +1,54 @@
|
||||
/** @file
|
||||
Registers definition for Intel QuarkNcSocId.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __INTEL_QNC_REGS_H__
|
||||
#define __INTEL_QNC_REGS_H__
|
||||
|
||||
#include <QNCAccess.h>
|
||||
|
||||
//
|
||||
// PCI HostBridge Segment number
|
||||
//
|
||||
#define QNC_PCI_HOST_BRIDGE_SEGMENT_NUMBER 0
|
||||
|
||||
//
|
||||
// PCI RootBridge resource allocation's attribute
|
||||
//
|
||||
#define QNC_PCI_ROOT_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTE \
|
||||
EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
|
||||
|
||||
//
|
||||
// PCI HostBridge resource appeture
|
||||
//
|
||||
#define QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSBASE 0x0
|
||||
#define QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSLIMIT 0xff
|
||||
#define QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_TSEG_SIZE 0x10000000
|
||||
|
||||
//
|
||||
// PCI RootBridge configure port
|
||||
//
|
||||
#define QNC_PCI_ROOT_BRIDGE_CONFIGURATION_ADDRESS_PORT 0xCF8
|
||||
#define QNC_PCI_ROOT_BRIDGE_CONFIGURATION_DATA_PORT 0xCFC
|
||||
|
||||
//
|
||||
// PCI Rootbridge's support feature
|
||||
//
|
||||
#define QNC_PCI_ROOT_BRIDGE_SUPPORTED (EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \
|
||||
EFI_PCI_ATTRIBUTE_ISA_IO | \
|
||||
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | \
|
||||
EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
|
||||
EFI_PCI_ATTRIBUTE_VGA_IO)
|
||||
|
||||
#endif // __INTEL_QNC_REGS_H__
|
||||
290
QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
Normal file
290
QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
Normal file
@@ -0,0 +1,290 @@
|
||||
/** @file
|
||||
Library that provides QNC specific library services in PEI phase
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __INTEL_QNC_LIB_H__
|
||||
#define __INTEL_QNC_LIB_H__
|
||||
|
||||
/**
|
||||
This function initializes the QNC register before MRC.
|
||||
It sets RCBA, PMBASE, disable Watchdog timer and initialize QNC GPIO.
|
||||
If the function cannot complete it'll ASSERT().
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
PeiQNCPreMemInit (
|
||||
VOID
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
Used to check SCH if it's S3 state. Clear the register state after query.
|
||||
|
||||
@retval TRUE if it's S3 state.
|
||||
@retval FALSE if it's not S3 state.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
QNCCheckS3AndClearState (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Used to check SCH if system wakes up from power on reset. Clear the register state after query.
|
||||
|
||||
@retval TRUE if system wakes up from power on reset
|
||||
@retval FALSE if system does not wake up from power on reset
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
QNCCheckPowerOnResetAndClearState (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
This function is used to clear SMI and wake status.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCClearSmiAndWake (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Used to initialize the QNC register after MRC.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
PeiQNCPostMemInit (
|
||||
VOID
|
||||
);
|
||||
|
||||
/** Send DRAM Ready opcode.
|
||||
|
||||
@param[in] OpcodeParam Parameter to DRAM ready opcode.
|
||||
|
||||
@retval VOID
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCSendOpcodeDramReady (
|
||||
IN UINT32 OpcodeParam
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
Relocate RMU Main binary to memory after MRC to improve performance.
|
||||
|
||||
@param[in] DestBaseAddress - Specify the new memory address for the RMU Main binary.
|
||||
@param[in] SrcBaseAddress - Specify the current memory address for the RMU Main binary.
|
||||
@param[in] Size - Specify size of the RMU Main binary.
|
||||
|
||||
@retval VOID
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
RmuMainRelocation (
|
||||
IN CONST UINT32 DestBaseAddress,
|
||||
IN CONST UINT32 SrcBaseAddress,
|
||||
IN CONST UINTN Size
|
||||
);
|
||||
|
||||
/**
|
||||
Get the total memory size
|
||||
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
QNCGetTotalMemorysize (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Get the memory range of TSEG.
|
||||
The TSEG's memory is below TOLM.
|
||||
|
||||
@param[out] BaseAddress The base address of TSEG's memory range
|
||||
@param[out] MemorySize The size of TSEG's memory range
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCGetTSEGMemoryRange (
|
||||
OUT UINT64 *BaseAddress,
|
||||
OUT UINT64 *MemorySize
|
||||
);
|
||||
|
||||
/**
|
||||
Updates the PAM registers in the MCH for the requested range and mode.
|
||||
|
||||
@param Start The start address of the memory region
|
||||
@param Length The length, in bytes, of the memory region
|
||||
@param ReadEnable Pointer to the boolean variable on whether to enable read for legacy memory section.
|
||||
If NULL, then read attribute will not be touched by this call.
|
||||
@param ReadEnable Pointer to the boolean variable on whether to enable write for legacy memory section.
|
||||
If NULL, then write attribute will not be touched by this call.
|
||||
@param Granularity A pointer to granularity, in bytes, that the PAM registers support
|
||||
|
||||
@retval RETURN_SUCCESS The PAM registers in the MCH were updated
|
||||
@retval RETURN_INVALID_PARAMETER The memory range is not valid in legacy region.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
QNCLegacyRegionManipulation (
|
||||
IN UINT32 Start,
|
||||
IN UINT32 Length,
|
||||
IN BOOLEAN *ReadEnable,
|
||||
IN BOOLEAN *WriteEnable,
|
||||
OUT UINT32 *Granularity
|
||||
);
|
||||
|
||||
/**
|
||||
Do early init of pci express rootports on Soc.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
PciExpressEarlyInit (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Complete initialization of all the pci express rootports on Soc.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciExpressInit (
|
||||
);
|
||||
|
||||
/**
|
||||
Determine if QNC is supported.
|
||||
|
||||
@retval FALSE QNC is not supported.
|
||||
@retval TRUE QNC is supported.
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
IsQncSupported (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Get the DeviceId of the SoC
|
||||
|
||||
@retval PCI DeviceId of the SoC
|
||||
**/
|
||||
UINT16
|
||||
EFIAPI
|
||||
QncGetSocDeviceId (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Enable SMI detection of legacy flash access violations.
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QncEnableLegacyFlashAccessViolationSmi (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Setup RMU Thermal sensor registers for Vref mode.
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCThermalSensorSetVRefMode (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Setup RMU Thermal sensor registers for Ratiometric mode.
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCThermalSensorSetRatiometricMode (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Setup RMU Thermal sensor trip point values.
|
||||
|
||||
@param[in] CatastrophicTripOnDegreesCelsius - Catastrophic set trip point threshold.
|
||||
@param[in] HotTripOnDegreesCelsius - Hot set trip point threshold.
|
||||
@param[in] HotTripOffDegreesCelsius - Hot clear trip point threshold.
|
||||
|
||||
@retval VOID
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
QNCThermalSensorSetTripValues (
|
||||
IN CONST UINTN CatastrophicTripOnDegreesCelsius,
|
||||
IN CONST UINTN HotTripOnDegreesCelsius,
|
||||
IN CONST UINTN HotTripOffDegreesCelsius
|
||||
);
|
||||
|
||||
/**
|
||||
Enable RMU Thermal sensor with a Catastrophic Trip point.
|
||||
|
||||
@retval EFI_SUCCESS Trip points setup.
|
||||
@retval EFI_INVALID_PARAMETER Invalid trip point value.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
QNCThermalSensorEnableWithCatastrophicTrip (
|
||||
IN CONST UINTN CatastrophicTripOnDegreesCelsius
|
||||
);
|
||||
|
||||
/**
|
||||
Lock all RMU Thermal sensor control & trip point registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCThermalSensorLockAllRegisters (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Set chipset policy for double bit ECC error.
|
||||
|
||||
@param[in] PolicyValue Policy to config on double bit ECC error.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCPolicyDblEccBitErr (
|
||||
IN CONST UINT32 PolicyValue
|
||||
);
|
||||
|
||||
/**
|
||||
Determine if running on secure Quark hardware Sku.
|
||||
|
||||
@retval FALSE Base Quark Sku or unprovisioned Secure Sku running.
|
||||
@retval TRUE Provisioned SecureSku hardware running.
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
QncIsSecureProvisionedSku (
|
||||
VOID
|
||||
);
|
||||
#endif
|
||||
|
||||
167
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
Normal file
167
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
Normal file
@@ -0,0 +1,167 @@
|
||||
/** @file
|
||||
Library functions for Setting QNC internal network port
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __QNC_ACCESS_LIB_H__
|
||||
#define __QNC_ACCESS_LIB_H__
|
||||
|
||||
#include <IntelQNCRegs.h>
|
||||
|
||||
#define MESSAGE_READ_DW(Port, Reg) \
|
||||
(UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
|
||||
|
||||
#define MESSAGE_WRITE_DW(Port, Reg) \
|
||||
(UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
|
||||
|
||||
#define ALT_MESSAGE_READ_DW(Port, Reg) \
|
||||
(UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
|
||||
|
||||
#define ALT_MESSAGE_WRITE_DW(Port, Reg) \
|
||||
(UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
|
||||
|
||||
#define MESSAGE_IO_READ_DW(Port, Reg) \
|
||||
(UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
|
||||
|
||||
#define MESSAGE_IO_WRITE_DW(Port, Reg) \
|
||||
(UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
|
||||
|
||||
#define MESSAGE_SHADOW_DW(Port, Reg) \
|
||||
(UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
|
||||
|
||||
|
||||
/**
|
||||
Read required data from QNC internal message network
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
QNCPortRead(
|
||||
UINT8 Port,
|
||||
UINT32 RegAddress
|
||||
);
|
||||
|
||||
/**
|
||||
Write prepared data into QNC internal message network.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCPortWrite (
|
||||
UINT8 Port,
|
||||
UINT32 RegAddress,
|
||||
UINT32 WriteValue
|
||||
);
|
||||
|
||||
/**
|
||||
Read required data from QNC internal message network
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
QNCAltPortRead(
|
||||
UINT8 Port,
|
||||
UINT32 RegAddress
|
||||
);
|
||||
|
||||
/**
|
||||
Write prepared data into QNC internal message network.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCAltPortWrite (
|
||||
UINT8 Port,
|
||||
UINT32 RegAddress,
|
||||
UINT32 WriteValue
|
||||
);
|
||||
|
||||
/**
|
||||
Read required data from QNC internal message network
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
QNCPortIORead(
|
||||
UINT8 Port,
|
||||
UINT32 RegAddress
|
||||
);
|
||||
|
||||
/**
|
||||
Write prepared data into QNC internal message network.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCPortIOWrite (
|
||||
UINT8 Port,
|
||||
UINT32 RegAddress,
|
||||
UINT32 WriteValue
|
||||
);
|
||||
|
||||
/**
|
||||
This is for the special consideration for QNC MMIO write, as required by FWG,
|
||||
a reading must be performed after MMIO writing to ensure the expected write
|
||||
is processed and data is flushed into chipset
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
QNCMmIoWrite (
|
||||
UINT32 MmIoAddress,
|
||||
QNC_MEM_IO_WIDTH Width,
|
||||
UINT32 DataNumber,
|
||||
VOID *pData
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
QncHsmmcRead (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
QncHsmmcWrite (
|
||||
UINT32 WriteValue
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
QncImrWrite (
|
||||
UINT32 ImrBaseOffset,
|
||||
UINT32 ImrLow,
|
||||
UINT32 ImrHigh,
|
||||
UINT32 ImrReadMask,
|
||||
UINT32 ImrWriteMask
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
QncIClkAndThenOr (
|
||||
UINT32 RegAddress,
|
||||
UINT32 AndValue,
|
||||
UINT32 OrValue
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
QncIClkOr (
|
||||
UINT32 RegAddress,
|
||||
UINT32 OrValue
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
QncGetPciExpressBaseAddress (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif
|
||||
63
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
Normal file
63
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
Normal file
@@ -0,0 +1,63 @@
|
||||
/** @file
|
||||
QNC Smm Library Services header file.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __QNC_SMM_LIB_H__
|
||||
#define __QNC_SMM_LIB_H__
|
||||
|
||||
/**
|
||||
This routine is the chipset code that accepts a request to "open" a region of SMRAM.
|
||||
The region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
|
||||
The use of "open" means that the memory is visible from all boot-service
|
||||
and SMM agents.
|
||||
|
||||
@retval FALSE Cannot open a locked SMRAM region
|
||||
@retval TRUE Success to open SMRAM region.
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
QNCOpenSmramRegion (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
This routine is the chipset code that accepts a request to "close" a region of SMRAM.
|
||||
The region could be legacy AB or TSEG near top of physical memory.
|
||||
The use of "close" means that the memory is only visible from SMM agents,
|
||||
not from BS or RT code.
|
||||
|
||||
@retval FALSE Cannot open a locked SMRAM region
|
||||
@retval TRUE Success to open SMRAM region.
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
QNCCloseSmramRegion (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
This routine is the chipset code that accepts a request to "lock" SMRAM.
|
||||
The region could be legacy AB or TSEG near top of physical memory.
|
||||
The use of "lock" means that the memory can no longer be opened
|
||||
to BS state.
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
QNCLockSmramRegion (
|
||||
VOID
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
42
QuarkSocPkg/QuarkNorthCluster/Include/Ppi/QNCMemoryInit.h
Normal file
42
QuarkSocPkg/QuarkNorthCluster/Include/Ppi/QNCMemoryInit.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/** @file
|
||||
Memory Initialization PPI used in EFI PEI interface
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __QNC_MEMORY_INIT_H__
|
||||
#define __QNC_MEMORY_INIT_H__
|
||||
|
||||
#include "mrc.h"
|
||||
|
||||
#define PEI_QNC_MEMORY_INIT_PPI_GUID \
|
||||
{0x21ff1fee, 0xd33a, 0x4fce, {0xa6, 0x5e, 0x95, 0x5e, 0xa3, 0xc4, 0x1f, 0x40}}
|
||||
|
||||
|
||||
|
||||
|
||||
//
|
||||
// PPI Function Declarations
|
||||
//
|
||||
typedef
|
||||
VOID
|
||||
(EFIAPI *PEI_QNC_MEMORY_INIT) (
|
||||
IN OUT MRCParams_t *MRCDATA
|
||||
);
|
||||
|
||||
typedef struct _PEI_QNC_MEMORY_INIT_PPI {
|
||||
PEI_QNC_MEMORY_INIT MrcStart;
|
||||
}PEI_QNC_MEMORY_INIT_PPI;
|
||||
|
||||
extern EFI_GUID gQNCMemoryInitPpiGuid;
|
||||
|
||||
#endif
|
||||
54
QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PchInfo.h
Normal file
54
QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PchInfo.h
Normal file
@@ -0,0 +1,54 @@
|
||||
/** @file
|
||||
This file defines the QNC Info Protocol.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
**/
|
||||
#ifndef _PCH_INFO_H_
|
||||
#define _PCH_INFO_H_
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gEfiQncInfoProtocolGuid;
|
||||
|
||||
//
|
||||
// Forward reference for ANSI C compatibility
|
||||
//
|
||||
typedef struct _EFI_QNC_INFO_PROTOCOL EFI_QNC_INFO_PROTOCOL;
|
||||
|
||||
//
|
||||
// Protocol revision number
|
||||
// Any backwards compatible changes to this protocol will result in an update in the revision number
|
||||
// Major changes will require publication of a new protocol
|
||||
//
|
||||
// Revision 1: Original version
|
||||
// Revision 2: Add RCVersion item to EFI_QNC_INFO_PROTOCOL
|
||||
//
|
||||
#define QNC_INFO_PROTOCOL_REVISION_1 1
|
||||
#define QNC_INFO_PROTOCOL_REVISION_2 2
|
||||
|
||||
//
|
||||
// RCVersion[7:0] is the release number.
|
||||
//
|
||||
#define QNC_RC_VERSION 0x01020000
|
||||
|
||||
//
|
||||
// Protocol definition
|
||||
//
|
||||
struct _EFI_QNC_INFO_PROTOCOL {
|
||||
UINT8 Revision;
|
||||
UINT8 BusNumber;
|
||||
UINT32 RCVersion;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,37 @@
|
||||
/** @file
|
||||
Protocol used for Platform Policy definition.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _PLATFORM_POLICY_H_
|
||||
#define _PLATFORM_POLICY_H_
|
||||
|
||||
typedef struct _EFI_PLATFORM_POLICY_PROTOCOL EFI_PLATFORM_POLICY_PROTOCOL;
|
||||
|
||||
#define EFI_PLATFORM_POLICY_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x2977064f, 0xab96, 0x4fa9, { 0x85, 0x45, 0xf9, 0xc4, 0x02, 0x51, 0xe0, 0x7f } \
|
||||
}
|
||||
|
||||
//
|
||||
// Protocol to describe various platform information. Add to this as needed.
|
||||
//
|
||||
struct _EFI_PLATFORM_POLICY_PROTOCOL {
|
||||
UINT8 NumRsvdSmbusAddresses;
|
||||
UINT8 *RsvdSmbusAddresses;
|
||||
};
|
||||
|
||||
extern EFI_GUID gEfiPlatformPolicyProtocolGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,90 @@
|
||||
/** @file
|
||||
This file defines the QNC S3 support Protocol.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
**/
|
||||
#ifndef _QNC_S3_SUPPORT_PROTOCOL_H_
|
||||
#define _QNC_S3_SUPPORT_PROTOCOL_H_
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gEfiQncS3SupportProtocolGuid;
|
||||
|
||||
//
|
||||
// Forward reference for ANSI C compatibility
|
||||
//
|
||||
typedef struct _EFI_QNC_S3_SUPPORT_PROTOCOL EFI_QNC_S3_SUPPORT_PROTOCOL;
|
||||
|
||||
typedef enum {
|
||||
QncS3ItemTypeInitPcieRootPortDownstream,
|
||||
QncS3ItemTypeMax
|
||||
} EFI_QNC_S3_DISPATCH_ITEM_TYPE;
|
||||
|
||||
//
|
||||
// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI
|
||||
// plug 4 to ParameterSize in PEIM if you really need it
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Reserved;
|
||||
} EFI_QNC_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM;
|
||||
|
||||
typedef union {
|
||||
EFI_QNC_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM PcieRootPortData;
|
||||
} EFI_DISPATCH_CONTEXT_UNION;
|
||||
|
||||
typedef struct {
|
||||
EFI_QNC_S3_DISPATCH_ITEM_TYPE Type;
|
||||
VOID *Parameter;
|
||||
} EFI_QNC_S3_DISPATCH_ITEM;
|
||||
|
||||
//
|
||||
// Member functions
|
||||
//
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_QNC_S3_SUPPORT_SET_S3_DISPATCH_ITEM) (
|
||||
IN EFI_QNC_S3_SUPPORT_PROTOCOL * This,
|
||||
IN EFI_QNC_S3_DISPATCH_ITEM * DispatchItem,
|
||||
OUT VOID **S3DispatchEntryPoint,
|
||||
OUT VOID **Context
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Set an item to be dispatched at S3 resume time. At the same time, the entry point
|
||||
of the QNC S3 support image is returned to be used in subsequent boot script save
|
||||
call
|
||||
|
||||
Arguments:
|
||||
|
||||
This - Pointer to the protocol instance.
|
||||
DispatchItem - The item to be dispatched.
|
||||
S3DispatchEntryPoint - The entry point of the QNC S3 support image.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_STATUS
|
||||
|
||||
--*/
|
||||
|
||||
//
|
||||
// Protocol definition
|
||||
//
|
||||
struct _EFI_QNC_S3_SUPPORT_PROTOCOL {
|
||||
EFI_QNC_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,121 @@
|
||||
/** @file
|
||||
Intel-only SMM Child Dispatcher Protocol.
|
||||
|
||||
This protocol provides a parent dispatch service for a collection of
|
||||
chipset-specific SMI source.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
|
||||
#ifndef __SMM_ICHN_DISPATCH2_H__
|
||||
#define __SMM_ICHN_DISPATCH2_H__
|
||||
|
||||
//
|
||||
// Share some common definitions with Framework SMM
|
||||
//
|
||||
#include <Protocol/SmmIchnDispatch.h>
|
||||
|
||||
#include <PiSmm.h>
|
||||
|
||||
//
|
||||
// Global ID for the ICH SMI Protocol
|
||||
//
|
||||
#define EFI_SMM_ICHN_DISPATCH2_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xadf3a128, 0x416d, 0x4060, {0x8d, 0xdf, 0x30, 0xa1, 0xd7, 0xaa, 0xb6, 0x99 } \
|
||||
}
|
||||
|
||||
typedef struct _EFI_SMM_ICHN_DISPATCH2_PROTOCOL EFI_SMM_ICHN_DISPATCH2_PROTOCOL;
|
||||
|
||||
typedef struct {
|
||||
EFI_SMM_ICHN_SMI_TYPE Type;
|
||||
} EFI_SMM_ICHN_REGISTER_CONTEXT;
|
||||
|
||||
//
|
||||
// Member functions
|
||||
//
|
||||
/**
|
||||
Register a child SMI source dispatch function with a parent SMM driver
|
||||
|
||||
@param This Protocol instance pointer.
|
||||
@param DispatchFunction Pointer to dispatch function to be invoked for
|
||||
this SMI source
|
||||
@param RegisterContext Pointer to the dispatch function's context.
|
||||
The caller fills this context in before calling
|
||||
the register function to indicate to the register
|
||||
function the ICHN SMI source for which the dispatch
|
||||
function should be invoked.
|
||||
@param DispatchHandle Handle generated by the dispatcher to track the
|
||||
function instance.
|
||||
|
||||
@retval EFI_SUCCESS The dispatch function has been successfully
|
||||
registered and the SMI source has been enabled.
|
||||
@retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
|
||||
@retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this
|
||||
child.
|
||||
@retval EFI_INVALID_PARAMETER RegisterContext is invalid. The ICHN input value
|
||||
is not within valid range.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SMM_ICHN_DISPATCH2_REGISTER) (
|
||||
IN CONST EFI_SMM_ICHN_DISPATCH2_PROTOCOL *This,
|
||||
IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
|
||||
IN OUT EFI_SMM_ICHN_REGISTER_CONTEXT *RegisterContext,
|
||||
OUT EFI_HANDLE *DispatchHandle
|
||||
);
|
||||
|
||||
/**
|
||||
Unregister a child SMI source dispatch function with a parent SMM driver
|
||||
|
||||
@param This Protocol instance pointer.
|
||||
@param DispatchHandle Handle of dispatch function to deregister.
|
||||
|
||||
@retval EFI_SUCCESS The dispatch function has been successfully
|
||||
unregistered and the SMI source has been disabled
|
||||
if there are no other registered child dispatch
|
||||
functions for this SMI source.
|
||||
@retval EFI_INVALID_PARAMETER Handle is invalid.
|
||||
@retval other
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SMM_ICHN_DISPATCH2_UNREGISTER) (
|
||||
IN EFI_SMM_ICHN_DISPATCH2_PROTOCOL *This,
|
||||
IN EFI_HANDLE DispatchHandle
|
||||
);
|
||||
|
||||
//
|
||||
// Interface structure for the SMM Ich n specific SMI Dispatch Protocol
|
||||
//
|
||||
/**
|
||||
@par Protocol Description:
|
||||
Provides a parent dispatch service for ICH SMI sources.
|
||||
|
||||
@param Register
|
||||
Installs a child service to be dispatched by this protocol.
|
||||
|
||||
@param UnRegister
|
||||
Removes a child service dispatched by this protocol.
|
||||
|
||||
**/
|
||||
struct _EFI_SMM_ICHN_DISPATCH2_PROTOCOL {
|
||||
EFI_SMM_ICHN_DISPATCH2_REGISTER Register;
|
||||
EFI_SMM_ICHN_DISPATCH2_UNREGISTER UnRegister;
|
||||
};
|
||||
|
||||
extern EFI_GUID gEfiSmmIchnDispatch2ProtocolGuid;
|
||||
|
||||
#endif
|
||||
351
QuarkSocPkg/QuarkNorthCluster/Include/Protocol/Spi.h
Normal file
351
QuarkSocPkg/QuarkNorthCluster/Include/Protocol/Spi.h
Normal file
@@ -0,0 +1,351 @@
|
||||
/** @file
|
||||
This file defines the EFI SPI Protocol which implements the
|
||||
Intel(R) ICH SPI Host Controller Compatibility Interface.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
**/
|
||||
#ifndef _SPI_H_
|
||||
#define _SPI_H_
|
||||
|
||||
//
|
||||
// Define the SPI protocol GUID
|
||||
//
|
||||
// EDK and EDKII have different GUID formats
|
||||
//
|
||||
#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
|
||||
#define EFI_SPI_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \
|
||||
}
|
||||
#define EFI_SMM_SPI_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \
|
||||
}
|
||||
#else
|
||||
#define EFI_SPI_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x1156efc6, 0xea32, 0x4396, \
|
||||
{ \
|
||||
0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \
|
||||
} \
|
||||
}
|
||||
#define EFI_SMM_SPI_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xD9072C35, 0xEB8F, 0x43ad, \
|
||||
{ \
|
||||
0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \
|
||||
} \
|
||||
}
|
||||
#endif
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gEfiSpiProtocolGuid;
|
||||
extern EFI_GUID gEfiSmmSpiProtocolGuid;
|
||||
|
||||
//
|
||||
// Forward reference for ANSI C compatibility
|
||||
//
|
||||
typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;
|
||||
|
||||
//
|
||||
// SPI protocol data structures and definitions
|
||||
//
|
||||
//
|
||||
// Number of Prefix Opcodes allowed on the SPI interface
|
||||
//
|
||||
#define SPI_NUM_PREFIX_OPCODE 2
|
||||
|
||||
//
|
||||
// Number of Opcodes in the Opcode Menu
|
||||
//
|
||||
#define SPI_NUM_OPCODE 8
|
||||
|
||||
#ifdef SERVER_BIOS_FLAG
|
||||
//
|
||||
// SPI default opcode slots
|
||||
//
|
||||
#define SPI_OPCODE_JEDEC_ID_INDEX 0
|
||||
#endif // SERVER_BIOS_FLAG
|
||||
|
||||
//
|
||||
// Opcode Type
|
||||
// EnumSpiOpcodeCommand: Command without address
|
||||
// EnumSpiOpcodeRead: Read with address
|
||||
// EnumSpiOpcodeWrite: Write with address
|
||||
//
|
||||
typedef enum {
|
||||
EnumSpiOpcodeReadNoAddr,
|
||||
EnumSpiOpcodeWriteNoAddr,
|
||||
EnumSpiOpcodeRead,
|
||||
EnumSpiOpcodeWrite,
|
||||
EnumSpiOpcodeMax
|
||||
} SPI_OPCODE_TYPE;
|
||||
|
||||
typedef enum {
|
||||
EnumSpiCycle20MHz,
|
||||
EnumSpiCycle33MHz,
|
||||
EnumSpiCycle66MHz, // not supported by PCH
|
||||
EnumSpiCycle50MHz,
|
||||
EnumSpiCycleMax
|
||||
} SPI_CYCLE_FREQUENCY;
|
||||
|
||||
typedef enum {
|
||||
EnumSpiRegionAll,
|
||||
EnumSpiRegionBios,
|
||||
EnumSpiRegionMe,
|
||||
EnumSpiRegionGbE,
|
||||
EnumSpiRegionDescriptor,
|
||||
EnumSpiRegionPlatformData,
|
||||
EnumSpiRegionMax
|
||||
} SPI_REGION_TYPE;
|
||||
|
||||
//
|
||||
// Hardware Sequencing required operations (as listed in CougarPoint EDS Table 5-55: "Hardware
|
||||
// Sequencing Commands and Opcode Requirements"
|
||||
//
|
||||
typedef enum {
|
||||
EnumSpiOperationWriteStatus,
|
||||
EnumSpiOperationProgramData_1_Byte,
|
||||
EnumSpiOperationProgramData_64_Byte,
|
||||
EnumSpiOperationReadData,
|
||||
EnumSpiOperationWriteDisable,
|
||||
EnumSpiOperationReadStatus,
|
||||
EnumSpiOperationWriteEnable,
|
||||
EnumSpiOperationFastRead,
|
||||
EnumSpiOperationEnableWriteStatus,
|
||||
EnumSpiOperationErase_256_Byte,
|
||||
EnumSpiOperationErase_4K_Byte,
|
||||
EnumSpiOperationErase_8K_Byte,
|
||||
EnumSpiOperationErase_64K_Byte,
|
||||
EnumSpiOperationFullChipErase,
|
||||
EnumSpiOperationJedecId,
|
||||
EnumSpiOperationDualOutputFastRead,
|
||||
EnumSpiOperationDiscoveryParameters,
|
||||
EnumSpiOperationOther,
|
||||
EnumSpiOperationMax
|
||||
} SPI_OPERATION;
|
||||
|
||||
//
|
||||
// Opcode menu entries
|
||||
// Type Operation Type (value to be programmed to the OPTYPE register)
|
||||
// Code The opcode (value to be programmed to the OPMENU register)
|
||||
// Frequency The expected frequency to be used (value to be programmed to the SSFC
|
||||
// Register)
|
||||
// Operation Which Hardware Sequencing required operation this opcode respoinds to.
|
||||
// The required operations are listed in EDS Table 5-55: "Hardware
|
||||
// Sequencing Commands and Opcode Requirements"
|
||||
// If the opcode does not corresponds to any operation listed, use
|
||||
// EnumSpiOperationOther
|
||||
//
|
||||
typedef struct _SPI_OPCODE_MENU_ENTRY {
|
||||
SPI_OPCODE_TYPE Type;
|
||||
UINT8 Code;
|
||||
SPI_CYCLE_FREQUENCY Frequency;
|
||||
SPI_OPERATION Operation;
|
||||
} SPI_OPCODE_MENU_ENTRY;
|
||||
|
||||
//
|
||||
// Initialization data table loaded to the SPI host controller
|
||||
// VendorId Vendor ID of the SPI device
|
||||
// DeviceId0 Device ID0 of the SPI device
|
||||
// DeviceId1 Device ID1 of the SPI device
|
||||
// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller
|
||||
// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu
|
||||
// BiosStartOffset The offset of the start of the BIOS image relative to the flash device.
|
||||
// Please note this is a Flash Linear Address, NOT a memory space address.
|
||||
// This value is platform specific and depends on the system flash map.
|
||||
// This value is only used on non Descriptor mode.
|
||||
// BiosSize The the BIOS Image size in flash. This value is platform specific
|
||||
// and depends on the system flash map. Please note BIOS Image size may
|
||||
// be smaller than BIOS Region size (in Descriptor Mode) or the flash size
|
||||
// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be
|
||||
// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash
|
||||
// (in Non Descriptor Mode)
|
||||
//
|
||||
typedef struct _SPI_INIT_TABLE {
|
||||
UINT8 VendorId;
|
||||
UINT8 DeviceId0;
|
||||
UINT8 DeviceId1;
|
||||
UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];
|
||||
SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];
|
||||
UINTN BiosStartOffset;
|
||||
UINTN BiosSize;
|
||||
} SPI_INIT_TABLE;
|
||||
|
||||
//
|
||||
// Public Info struct to show current initialized state of the spi interface.
|
||||
// OpcodeIndex must be less then SPI_NUM_OPCODE for operation to be supported.
|
||||
//
|
||||
typedef struct _SPI_INIT_INFO {
|
||||
SPI_INIT_TABLE *InitTable;
|
||||
UINT8 JedecIdOpcodeIndex;
|
||||
UINT8 OtherOpcodeIndex;
|
||||
UINT8 WriteStatusOpcodeIndex;
|
||||
UINT8 ProgramOpcodeIndex;
|
||||
UINT8 ReadOpcodeIndex;
|
||||
UINT8 EraseOpcodeIndex;
|
||||
UINT8 ReadStatusOpcodeIndex;
|
||||
UINT8 FullChipEraseOpcodeIndex;
|
||||
} SPI_INIT_INFO;
|
||||
|
||||
//
|
||||
// Protocol member functions
|
||||
//
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SPI_INIT) (
|
||||
IN EFI_SPI_PROTOCOL * This,
|
||||
IN SPI_INIT_TABLE * InitTable
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Initializes the host controller to execute SPI commands.
|
||||
|
||||
Arguments:
|
||||
|
||||
This Pointer to the EFI_SPI_PROTOCOL instance.
|
||||
InitTable Pointer to caller-allocated buffer containing the SPI
|
||||
interface initialization table.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_SUCCESS Opcode initialization on the SPI host controller completed.
|
||||
EFI_ACCESS_DENIED The SPI configuration interface is locked.
|
||||
EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.
|
||||
EFI_DEVICE_ERROR Device error, operation failed.
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SPI_LOCK) (
|
||||
IN EFI_SPI_PROTOCOL * This
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Lock the SPI Static Configuration Interface.
|
||||
Once locked, the interface is no longer open for configuration changes.
|
||||
The lock state automatically clears on next system reset.
|
||||
|
||||
Arguments:
|
||||
|
||||
This Pointer to the EFI_SPI_PROTOCOL instance.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_SUCCESS Lock operation succeed.
|
||||
EFI_DEVICE_ERROR Device error, operation failed.
|
||||
EFI_ACCESS_DENIED The interface has already been locked.
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SPI_EXECUTE) (
|
||||
IN EFI_SPI_PROTOCOL * This,
|
||||
IN UINT8 OpcodeIndex,
|
||||
IN UINT8 PrefixOpcodeIndex,
|
||||
IN BOOLEAN DataCycle,
|
||||
IN BOOLEAN Atomic,
|
||||
IN BOOLEAN ShiftOut,
|
||||
IN UINTN Address,
|
||||
IN UINT32 DataByteCount,
|
||||
IN OUT UINT8 *Buffer,
|
||||
IN SPI_REGION_TYPE SpiRegionType
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Execute SPI commands from the host controller.
|
||||
|
||||
Arguments:
|
||||
|
||||
This Pointer to the EFI_SPI_PROTOCOL instance.
|
||||
OpcodeIndex Index of the command in the OpCode Menu.
|
||||
PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.
|
||||
DataCycle TRUE if the SPI cycle contains data
|
||||
Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.
|
||||
ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.
|
||||
Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform
|
||||
Region, this value specifies the offset from the Region Base; for BIOS Region,
|
||||
this value specifies the offset from the start of the BIOS Image. In Non
|
||||
Descriptor Mode, this value specifies the offset from the start of the BIOS Image.
|
||||
Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor
|
||||
Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is
|
||||
supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or
|
||||
the flash (in Non Descriptor Mode)
|
||||
DataByteCount Number of bytes in the data portion of the SPI cycle.
|
||||
Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
|
||||
SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,
|
||||
EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in
|
||||
Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode
|
||||
and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative
|
||||
to base of the 1st flash device (i.e., it is a Flash Linear Address).
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_SUCCESS Command succeed.
|
||||
EFI_INVALID_PARAMETER The parameters specified are not valid.
|
||||
EFI_UNSUPPORTED Command not supported.
|
||||
EFI_DEVICE_ERROR Device error, command aborts abnormally.
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SPI_INFO) (
|
||||
IN EFI_SPI_PROTOCOL *This,
|
||||
OUT SPI_INIT_INFO **InitInfoPtr
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Return info about SPI host controller, to help callers usage of Execute
|
||||
service.
|
||||
|
||||
If 0xff is returned as an opcode index in init info struct
|
||||
then device does not support the operation.
|
||||
|
||||
Arguments:
|
||||
|
||||
This Pointer to the EFI_SPI_PROTOCOL instance.
|
||||
InitInfoPtr Pointer to init info written to this memory location.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_SUCCESS Information returned.
|
||||
EFI_INVALID_PARAMETER Invalid parameter.
|
||||
EFI_NOT_READY Required resources not setup.
|
||||
Others Unexpected error happened.
|
||||
|
||||
--*/
|
||||
|
||||
//
|
||||
// Protocol definition
|
||||
//
|
||||
struct _EFI_SPI_PROTOCOL {
|
||||
EFI_SPI_INIT Init;
|
||||
EFI_SPI_LOCK Lock;
|
||||
EFI_SPI_EXECUTE Execute;
|
||||
EFI_SPI_INFO Info;
|
||||
};
|
||||
|
||||
#endif
|
||||
183
QuarkSocPkg/QuarkNorthCluster/Include/QNCAccess.h
Normal file
183
QuarkSocPkg/QuarkNorthCluster/Include/QNCAccess.h
Normal file
@@ -0,0 +1,183 @@
|
||||
/** @file
|
||||
Macros to simplify and abstract the interface to PCI configuration.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _QNC_ACCESS_H_
|
||||
#define _QNC_ACCESS_H_
|
||||
|
||||
#include "QuarkNcSocId.h"
|
||||
#include "QNCCommonDefinitions.h"
|
||||
|
||||
#define EFI_LPC_PCI_ADDRESS( Register ) \
|
||||
EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register)
|
||||
|
||||
//
|
||||
// QNC Controller PCI access macros
|
||||
//
|
||||
#define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0, PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK)
|
||||
|
||||
//
|
||||
// Device 0x1f, Function 0
|
||||
//
|
||||
|
||||
#define LpcPciCfg32( Register ) \
|
||||
QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
|
||||
|
||||
#define LpcPciCfg32Or( Register, OrData ) \
|
||||
QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
|
||||
|
||||
#define LpcPciCfg32And( Register, AndData ) \
|
||||
QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
|
||||
|
||||
#define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \
|
||||
QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
|
||||
|
||||
#define LpcPciCfg16( Register ) \
|
||||
QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
|
||||
|
||||
#define LpcPciCfg16Or( Register, OrData ) \
|
||||
QNCMmPci16Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
|
||||
|
||||
#define LpcPciCfg16And( Register, AndData ) \
|
||||
QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
|
||||
|
||||
#define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \
|
||||
QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
|
||||
|
||||
#define LpcPciCfg8( Register ) \
|
||||
QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
|
||||
|
||||
#define LpcPciCfg8Or( Register, OrData ) \
|
||||
QNCMmPci8Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
|
||||
|
||||
#define LpcPciCfg8And( Register, AndData ) \
|
||||
QNCMmPci8And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
|
||||
|
||||
#define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \
|
||||
QNCMmPci8AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
|
||||
|
||||
//
|
||||
// Root Complex Register Block
|
||||
//
|
||||
|
||||
#define MmRcrb32( Register ) \
|
||||
QNCMmio32( QNC_RCRB_BASE, Register )
|
||||
|
||||
#define MmRcrb32Or( Register, OrData ) \
|
||||
QNCMmio32Or( QNC_RCRB_BASE, Register, OrData )
|
||||
|
||||
#define MmRcrb32And( Register, AndData ) \
|
||||
QNCMmio32And( QNC_RCRB_BASE, Register, AndData )
|
||||
|
||||
#define MmRcrb32AndThenOr( Register, AndData, OrData ) \
|
||||
QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
|
||||
|
||||
#define MmRcrb16( Register ) \
|
||||
QNCMmio16( QNC_RCRB_BASE, Register )
|
||||
|
||||
#define MmRcrb16Or( Register, OrData ) \
|
||||
QNCMmio16Or( QNC_RCRB_BASE, Register, OrData )
|
||||
|
||||
#define MmRcrb16And( Register, AndData ) \
|
||||
QNCMmio16And( QNC_RCRB_BASE, Register, AndData )
|
||||
|
||||
#define MmRcrb16AndThenOr( Register, AndData, OrData ) \
|
||||
QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
|
||||
|
||||
#define MmRcrb8( Register ) \
|
||||
QNCMmio8( QNC_RCRB_BASE, Register )
|
||||
|
||||
#define MmRcrb8Or( Register, OrData ) \
|
||||
QNCMmio8Or( QNC_RCRB_BASE, Register, OrData )
|
||||
|
||||
#define MmRcrb8And( Register, AndData ) \
|
||||
QNCMmio8And( QNC_RCRB_BASE, Register, AndData )
|
||||
|
||||
#define MmRcrb8AndThenOr( Register, AndData, OrData ) \
|
||||
QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
|
||||
|
||||
//
|
||||
// Memory Controller PCI access macros
|
||||
//
|
||||
|
||||
//
|
||||
// Device 0, Function 0
|
||||
//
|
||||
|
||||
#define McD0PciCfg64(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg64Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg64And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg64AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD0PciCfg32(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg32Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg32And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg32AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD0PciCfg16(Register) QNCMmPci16 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg16Or(Register, OrData) QNCMmPci16Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg16And(Register, AndData) QNCMmPci16And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg16AndThenOr(Register, AndData, OrData) QNCMmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD0PciCfg8(Register) QNCMmPci8 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg8Or(Register, OrData) QNCMmPci8Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg8And(Register, AndData) QNCMmPci8And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) QNCMmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
|
||||
//
|
||||
// Memory Controller Hub Memory Mapped IO register access ???
|
||||
//
|
||||
#define MCH_REGION_BASE (McD0PciCfg64 (MC_MCHBAR_OFFSET) & ~BIT0)
|
||||
#define McMmioAddress(Register) ((UINTN) MCH_REGION_BASE + (UINTN) (Register))
|
||||
|
||||
#define McMmio32Ptr(Register) ((volatile UINT32*) McMmioAddress (Register))
|
||||
#define McMmio64Ptr(Register) ((volatile UINT64*) McMmioAddress (Register))
|
||||
|
||||
#define McMmio64(Register) *McMmio64Ptr( Register )
|
||||
#define McMmio64Or(Register, OrData) (McMmio64 (Register) |= (UINT64)(OrData))
|
||||
#define McMmio64And(Register, AndData) (McMmio64 (Register) &= (UINT64)(AndData))
|
||||
#define McMmio64AndThenOr(Register, AndData, OrData) (McMmio64 ( Register ) = (McMmio64( Register ) & (UINT64)(AndData)) | (UINT64)(OrData))
|
||||
|
||||
#define McMmio32(Register) *McMmio32Ptr (Register)
|
||||
#define McMmio32Or(Register, OrData) (McMmio32 (Register) |= (UINT32)(OrData))
|
||||
#define McMmio32And(Register, AndData) (McMmio32 (Register) &= (UINT32)(AndData))
|
||||
#define McMmio32AndThenOr(Register, AndData, OrData) (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData))
|
||||
|
||||
#define McMmio16Ptr(Register) ((volatile UINT16*) McMmioAddress (Register))
|
||||
#define McMmio16(Register) *McMmio16Ptr (Register)
|
||||
#define McMmio16Or(Register, OrData) (McMmio16 (Register) |= (UINT16) (OrData))
|
||||
#define McMmio16And(Register, AndData) (McMmio16 (Register) &= (UINT16) (AndData))
|
||||
#define McMmio16AndThenOr(Register, AndData, OrData) (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData))
|
||||
|
||||
#define McMmio8Ptr(Register) ((volatile UINT8 *)McMmioAddress (Register))
|
||||
#define McMmio8(Register) *McMmio8Ptr (Register)
|
||||
#define McMmio8Or(Register, OrData) (McMmio8 (Register) |= (UINT8) (OrData))
|
||||
#define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8) (AndData))
|
||||
#define McMmio8AndThenOr(Register, AndData, OrData) (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))
|
||||
|
||||
//
|
||||
// QNC memory mapped related data structure deifinition
|
||||
//
|
||||
typedef enum {
|
||||
QNCMmioWidthUint8 = 0,
|
||||
QNCMmioWidthUint16 = 1,
|
||||
QNCMmioWidthUint32 = 2,
|
||||
QNCMmioWidthUint64 = 3,
|
||||
QNCMmioWidthMaximum
|
||||
} QNC_MEM_IO_WIDTH;
|
||||
|
||||
#endif
|
||||
|
||||
356
QuarkSocPkg/QuarkNorthCluster/Include/QNCCommonDefinitions.h
Normal file
356
QuarkSocPkg/QuarkNorthCluster/Include/QNCCommonDefinitions.h
Normal file
@@ -0,0 +1,356 @@
|
||||
/** @file
|
||||
This header file provides common definitions just for MCH using to avoid including extra module's file.
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _QNC_COMMON_DEFINITIONS_H_
|
||||
#define _QNC_COMMON_DEFINITIONS_H_
|
||||
|
||||
//
|
||||
// PCI CONFIGURATION MAP REGISTER OFFSETS
|
||||
//
|
||||
#ifndef PCI_VID
|
||||
#define PCI_VID 0x0000 // Vendor ID Register
|
||||
#define PCI_DID 0x0002 // Device ID Register
|
||||
#define PCI_CMD 0x0004 // PCI Command Register
|
||||
#define PCI_STS 0x0006 // PCI Status Register
|
||||
#define PCI_RID 0x0008 // Revision ID Register
|
||||
#define PCI_IFT 0x0009 // Interface Type
|
||||
#define PCI_SCC 0x000A // Sub Class Code Register
|
||||
#define PCI_BCC 0x000B // Base Class Code Register
|
||||
#define PCI_CLS 0x000C // Cache Line Size
|
||||
#define PCI_PMLT 0x000D // Primary Master Latency Timer
|
||||
#define PCI_HDR 0x000E // Header Type Register
|
||||
#define PCI_BIST 0x000F // Built in Self Test Register
|
||||
#define PCI_BAR0 0x0010 // Base Address Register 0
|
||||
#define PCI_BAR1 0x0014 // Base Address Register 1
|
||||
#define PCI_BAR2 0x0018 // Base Address Register 2
|
||||
#define PCI_PBUS 0x0018 // Primary Bus Number Register
|
||||
#define PCI_SBUS 0x0019 // Secondary Bus Number Register
|
||||
#define PCI_SUBUS 0x001A // Subordinate Bus Number Register
|
||||
#define PCI_SMLT 0x001B // Secondary Master Latency Timer
|
||||
#define PCI_BAR3 0x001C // Base Address Register 3
|
||||
#define PCI_IOBASE 0x001C // I/O base Register
|
||||
#define PCI_IOLIMIT 0x001D // I/O Limit Register
|
||||
#define PCI_SECSTATUS 0x001E // Secondary Status Register
|
||||
#define PCI_BAR4 0x0020 // Base Address Register 4
|
||||
#define PCI_MEMBASE 0x0020 // Memory Base Register
|
||||
#define PCI_MEMLIMIT 0x0022 // Memory Limit Register
|
||||
#define PCI_BAR5 0x0024 // Base Address Register 5
|
||||
#define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register
|
||||
#define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register
|
||||
#define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits
|
||||
#define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits
|
||||
#define PCI_SVID 0x002C // Subsystem Vendor ID
|
||||
#define PCI_SID 0x002E // Subsystem ID
|
||||
#define PCI_IOBASE_U 0x0030 // I/O base Upper Register
|
||||
#define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register
|
||||
#define PCI_CAPP 0x0034 // Capabilities Pointer
|
||||
#define PCI_EROM 0x0038 // Expansion ROM Base Address
|
||||
#define PCI_INTLINE 0x003C // Interrupt Line Register
|
||||
#define PCI_INTPIN 0x003D // Interrupt Pin Register
|
||||
#define PCI_MAXGNT 0x003E // Max Grant Register
|
||||
#define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register
|
||||
#define PCI_MAXLAT 0x003F // Max Latency Register
|
||||
#endif
|
||||
//
|
||||
// Bit Difinitions
|
||||
//
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x0001
|
||||
#define BIT1 0x0002
|
||||
#define BIT2 0x0004
|
||||
#define BIT3 0x0008
|
||||
#define BIT4 0x0010
|
||||
#define BIT5 0x0020
|
||||
#define BIT6 0x0040
|
||||
#define BIT7 0x0080
|
||||
#define BIT8 0x0100
|
||||
#define BIT9 0x0200
|
||||
#define BIT10 0x0400
|
||||
#define BIT11 0x0800
|
||||
#define BIT12 0x1000
|
||||
#define BIT13 0x2000
|
||||
#define BIT14 0x4000
|
||||
#define BIT15 0x8000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// Common Memory mapped Io access macros ------------------------------------------
|
||||
//
|
||||
#define QNCMmioAddress( BaseAddr, Register ) \
|
||||
( (UINTN)BaseAddr + \
|
||||
(UINTN)(Register) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT64
|
||||
//
|
||||
#define QNCMmio64Ptr( BaseAddr, Register ) \
|
||||
( (volatile UINT64 *)QNCMmioAddress( BaseAddr, Register ) )
|
||||
|
||||
#define QNCMmio64( BaseAddr, Register ) \
|
||||
*QNCMmio64Ptr( BaseAddr, Register )
|
||||
|
||||
#define QNCMmio64Or( BaseAddr, Register, OrData ) \
|
||||
QNCMmio64( BaseAddr, Register ) = \
|
||||
(UINT64) ( \
|
||||
QNCMmio64( BaseAddr, Register ) | \
|
||||
(UINT64)(OrData) \
|
||||
)
|
||||
|
||||
#define QNCMmio64And( BaseAddr, Register, AndData ) \
|
||||
QNCMmio64( BaseAddr, Register ) = \
|
||||
(UINT64) ( \
|
||||
QNCMmio64( BaseAddr, Register ) & \
|
||||
(UINT64)(AndData) \
|
||||
)
|
||||
|
||||
#define QNCMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \
|
||||
QNCMmio64( BaseAddr, Register ) = \
|
||||
(UINT64) ( \
|
||||
( QNCMmio64( BaseAddr, Register ) & \
|
||||
(UINT64)(AndData) \
|
||||
) | \
|
||||
(UINT64)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT32
|
||||
//
|
||||
#define QNCMmio32Ptr( BaseAddr, Register ) \
|
||||
( (volatile UINT32 *)QNCMmioAddress( BaseAddr, Register ) )
|
||||
|
||||
#define QNCMmio32( BaseAddr, Register ) \
|
||||
*QNCMmio32Ptr( BaseAddr, Register )
|
||||
|
||||
#define QNCMmio32Or( BaseAddr, Register, OrData ) \
|
||||
QNCMmio32( BaseAddr, Register ) = \
|
||||
(UINT32) ( \
|
||||
QNCMmio32( BaseAddr, Register ) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
|
||||
#define QNCMmio32And( BaseAddr, Register, AndData ) \
|
||||
QNCMmio32( BaseAddr, Register ) = \
|
||||
(UINT32) ( \
|
||||
QNCMmio32( BaseAddr, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
)
|
||||
|
||||
#define QNCMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
|
||||
QNCMmio32( BaseAddr, Register ) = \
|
||||
(UINT32) ( \
|
||||
( QNCMmio32( BaseAddr, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
//
|
||||
// UINT16
|
||||
//
|
||||
|
||||
#define QNCMmio16Ptr( BaseAddr, Register ) \
|
||||
( (volatile UINT16 *)QNCMmioAddress( BaseAddr, Register ) )
|
||||
|
||||
#define QNCMmio16( BaseAddr, Register ) \
|
||||
*QNCMmio16Ptr( BaseAddr, Register )
|
||||
|
||||
#define QNCMmio16Or( BaseAddr, Register, OrData ) \
|
||||
QNCMmio16( BaseAddr, Register ) = \
|
||||
(UINT16) ( \
|
||||
QNCMmio16( BaseAddr, Register ) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
|
||||
#define QNCMmio16And( BaseAddr, Register, AndData ) \
|
||||
QNCMmio16( BaseAddr, Register ) = \
|
||||
(UINT16) ( \
|
||||
QNCMmio16( BaseAddr, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
)
|
||||
|
||||
#define QNCMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
|
||||
QNCMmio16( BaseAddr, Register ) = \
|
||||
(UINT16) ( \
|
||||
( QNCMmio16( BaseAddr, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
//
|
||||
// UINT8
|
||||
//
|
||||
#define QNCMmio8Ptr( BaseAddr, Register ) \
|
||||
( (volatile UINT8 *)QNCMmioAddress( BaseAddr, Register ) )
|
||||
|
||||
#define QNCMmio8( BaseAddr, Register ) \
|
||||
*QNCMmio8Ptr( BaseAddr, Register )
|
||||
|
||||
#define QNCMmio8Or( BaseAddr, Register, OrData ) \
|
||||
QNCMmio8( BaseAddr, Register ) = \
|
||||
(UINT8) ( \
|
||||
QNCMmio8( BaseAddr, Register ) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
#define QNCMmio8And( BaseAddr, Register, AndData ) \
|
||||
QNCMmio8( BaseAddr, Register ) = \
|
||||
(UINT8) ( \
|
||||
QNCMmio8( BaseAddr, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
)
|
||||
|
||||
#define QNCMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
|
||||
QNCMmio8( BaseAddr, Register ) = \
|
||||
(UINT8) ( \
|
||||
( QNCMmio8( BaseAddr, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// Common Memory mapped Pci access macros ------------------------------------------
|
||||
//
|
||||
|
||||
#define QNCMmPciAddress( Segment, Bus, Device, Function, Register ) \
|
||||
( (UINTN) QncGetPciExpressBaseAddress() + \
|
||||
(UINTN)(Bus << 20) + \
|
||||
(UINTN)(Device << 15) + \
|
||||
(UINTN)(Function << 12) + \
|
||||
(UINTN)(Register) \
|
||||
)
|
||||
|
||||
//
|
||||
// Macro to calculate the Pci device's base memory mapped address
|
||||
//
|
||||
#define PciDeviceMmBase( Bus, Device, Function) \
|
||||
( (UINTN) QncGetPciExpressBaseAddress () + \
|
||||
(UINTN)(Bus << 20) + \
|
||||
(UINTN)(Device << 15) + \
|
||||
(UINTN)(Function << 12) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT32
|
||||
//
|
||||
#define QNCMmPci32Ptr( Segment, Bus, Device, Function, Register ) \
|
||||
( (volatile UINT32 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )
|
||||
|
||||
#define QNCMmPci32( Segment, Bus, Device, Function, Register ) \
|
||||
*QNCMmPci32Ptr( Segment, Bus, Device, Function, Register )
|
||||
|
||||
#define QNCMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
|
||||
QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT32) ( \
|
||||
QNCMmPci32( Segment, Bus, Device, Function, Register ) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
|
||||
#define QNCMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
|
||||
QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT32) ( \
|
||||
QNCMmPci32( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
)
|
||||
|
||||
#define QNCMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
|
||||
QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT32) ( \
|
||||
( QNCMmPci32( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
//
|
||||
// UINT16
|
||||
//
|
||||
#define QNCMmPci16Ptr( Segment, Bus, Device, Function, Register ) \
|
||||
( (volatile UINT16 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )
|
||||
|
||||
#define QNCMmPci16( Segment, Bus, Device, Function, Register ) \
|
||||
*QNCMmPci16Ptr( Segment, Bus, Device, Function, Register )
|
||||
|
||||
#define QNCMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
|
||||
QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT16) ( \
|
||||
QNCMmPci16( Segment, Bus, Device, Function, Register ) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
|
||||
#define QNCMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
|
||||
QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT16) ( \
|
||||
QNCMmPci16( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
)
|
||||
|
||||
#define QNCMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
|
||||
QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT16) ( \
|
||||
( QNCMmPci16( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
//
|
||||
// UINT8
|
||||
//
|
||||
#define QNCMmPci8Ptr( Segment, Bus, Device, Function, Register ) \
|
||||
( (volatile UINT8 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )
|
||||
|
||||
#define QNCMmPci8( Segment, Bus, Device, Function, Register ) \
|
||||
*QNCMmPci8Ptr( Segment, Bus, Device, Function, Register )
|
||||
|
||||
#define QNCMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
|
||||
QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT8) ( \
|
||||
QNCMmPci8( Segment, Bus, Device, Function, Register ) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
#define QNCMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
|
||||
QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT8) ( \
|
||||
QNCMmPci8( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
)
|
||||
|
||||
#define QNCMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
|
||||
QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT8) ( \
|
||||
( QNCMmPci8( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
#endif
|
||||
757
QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
Normal file
757
QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
Normal file
@@ -0,0 +1,757 @@
|
||||
/** @file
|
||||
QuarkNcSocId Register Definitions
|
||||
|
||||
Copyright (c) 2013-2015 Intel Corporation.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _QUARK_NC_SOC_ID_H_
|
||||
#define _QUARK_NC_SOC_ID_H_
|
||||
|
||||
//
|
||||
// QNC GMCH Equates
|
||||
//
|
||||
|
||||
//
|
||||
// DEVICE 0 (Memroy Controller Hub)
|
||||
//
|
||||
#define MC_BUS PCI_BUS_NUMBER_QNC
|
||||
#define MC_DEV 0x00
|
||||
#define MC_FUN 0x00
|
||||
|
||||
#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID
|
||||
#define QUARK_MC_DEVICE_ID 0x0958
|
||||
#define QUARK2_MC_DEVICE_ID 0x12C0
|
||||
#define QNC_MC_REV_ID_A0 0x00
|
||||
|
||||
|
||||
//
|
||||
// MCR - B0:D0:F0:RD0h (WO)- Message control register
|
||||
// [31:24] Message opcode - D0 read; E0 write;
|
||||
// [23:16] Message port
|
||||
// [15:8 ] Message target register address
|
||||
// [ 7:4 ] Message write byte enable : F is enable
|
||||
// [ 3:0 ] Reserved
|
||||
//
|
||||
#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register
|
||||
// Always Set to 0xF0
|
||||
|
||||
//
|
||||
//MDR - B0:D0:F0:RD4h (RW)- Message data register
|
||||
//
|
||||
#define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register
|
||||
|
||||
//
|
||||
//MEA - B0:D0:F0:RD8h (RW)- Message extended address register
|
||||
//
|
||||
#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register
|
||||
|
||||
#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR
|
||||
#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR
|
||||
#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR
|
||||
|
||||
//
|
||||
// Misc Useful Macros
|
||||
//
|
||||
|
||||
#define LShift16(value) (value << 16)
|
||||
|
||||
//
|
||||
// QNC Message OpCodes and Attributes
|
||||
//
|
||||
#define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode
|
||||
#define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode
|
||||
|
||||
//
|
||||
// Alternative opcodes for the SCSS block
|
||||
//
|
||||
#define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode
|
||||
#define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode
|
||||
|
||||
//
|
||||
// QNC Message OpCodes and Attributes for IO
|
||||
//
|
||||
#define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode
|
||||
#define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode
|
||||
|
||||
|
||||
#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode
|
||||
|
||||
#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode
|
||||
#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode
|
||||
|
||||
//
|
||||
// QNC Message Ports and Registers
|
||||
//
|
||||
// Start of SB Port IDs
|
||||
#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00
|
||||
#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01
|
||||
#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03
|
||||
#define QUARK_NC_RMU_SB_PORT_ID 0x04
|
||||
#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05
|
||||
#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14
|
||||
#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16
|
||||
#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31
|
||||
#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33
|
||||
#define QUARK_ICLK_SB_PORT_ID 0x32
|
||||
#define QUARK_SCSS_CRU_SB_PORT_ID 0x34
|
||||
|
||||
//
|
||||
// Quark Memory Arbiter Registers.
|
||||
//
|
||||
#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register.
|
||||
#define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient
|
||||
#define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh.
|
||||
#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing.
|
||||
#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing.
|
||||
#define ASTATUS1_RASISED_BP (10)
|
||||
#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
#define ASTATUS0_RASISED_BP (8)
|
||||
#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
#define ASTATUS1_DEFAULT_BP (2)
|
||||
#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
#define ASTATUS0_DEFAULT_BP (0)
|
||||
#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
|
||||
//
|
||||
// Quark Memory Controller Registers.
|
||||
//
|
||||
#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register.
|
||||
#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC.
|
||||
|
||||
//
|
||||
// Quark Remote Management Unit Registers.
|
||||
//
|
||||
#define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address
|
||||
|
||||
#define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register.
|
||||
#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)
|
||||
#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)
|
||||
|
||||
#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1.
|
||||
#define OPTIONS_1_DMA_DISABLE (BIT0)
|
||||
|
||||
#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register.
|
||||
#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)
|
||||
#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
|
||||
|
||||
#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register.
|
||||
#define TS_ENABLE (BIT15)
|
||||
#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register.
|
||||
#define TS_HOT_TRIP_CLEAR_THOLD_BP 24
|
||||
#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)
|
||||
#define TS_CAT_TRIP_CLEAR_THOLD_BP 16
|
||||
#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)
|
||||
#define TS_HOT_TRIP_SET_THOLD_BP 8
|
||||
#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)
|
||||
#define TS_CAT_TRIP_SET_THOLD_BP 0
|
||||
#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)
|
||||
|
||||
#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50
|
||||
#define SCRUB_CFG_INTERVAL_SHIFT 0x00
|
||||
#define SCRUB_CFG_INTERVAL_MASK 0xFF
|
||||
#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08
|
||||
#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F
|
||||
#define SCRUB_CFG_ACTIVE (BIT13)
|
||||
#define SCRUB_CFG_INVALID 0x00000FFF
|
||||
|
||||
#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76
|
||||
#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77
|
||||
#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C
|
||||
|
||||
#define SCRUB_RESUME_MSG() ((UINT32)( \
|
||||
(QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \
|
||||
(QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
|
||||
0xF0))
|
||||
|
||||
#define SCRUB_PAUSE_MSG() ((UINT32)( \
|
||||
(QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \
|
||||
(QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
|
||||
0xF0))
|
||||
|
||||
//
|
||||
// Quark Memory Manager Registers
|
||||
//
|
||||
#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82
|
||||
#define BLOCK_ENABLE_PG (1 << 28)
|
||||
#define BLOCK_DISABLE_PG (1 << 29)
|
||||
#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19
|
||||
#define EnableIMRInt BIT31
|
||||
#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C
|
||||
#define EnableSMMInt BIT31
|
||||
#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20
|
||||
#define DRAM_NON_HOST_RQ_LIMIT_BP 0
|
||||
#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)
|
||||
|
||||
#define QUARK_NC_TOTAL_IMR_SET 0x8
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR1 0x44
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR2 0x48
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR4 0x50
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00
|
||||
#define IMR_LOCK BIT31
|
||||
#define IMR_EN BIT30
|
||||
#define IMRL_MASK 0x00FFFFFC
|
||||
#define IMRL_RESET 0x00000000
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01
|
||||
#define IMRH_MASK 0x00FFFFFC
|
||||
#define IMRH_RESET 0x00000000
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03
|
||||
#define IMRX_ALL_ACCESS 0xFFFFFFFF
|
||||
#define CPU_SNOOP BIT30
|
||||
#define RMU BIT29
|
||||
#define CPU0_NON_SMM BIT0
|
||||
|
||||
//
|
||||
// Quark Host Bridge Registers
|
||||
//
|
||||
#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls
|
||||
#define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge)
|
||||
#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control
|
||||
#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN
|
||||
#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN
|
||||
#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN
|
||||
#define SMM_CTL_EN (BIT3) // SMM enable
|
||||
#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN
|
||||
#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN
|
||||
#define SMM_LOCKED (BIT0) // SMM Locked
|
||||
#define SMM_START_MASK 0x0000FFF0
|
||||
#define SMM_END_MASK 0xFFF00000
|
||||
#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08
|
||||
#define HMBOUND_MASK 0x0FFFFF000
|
||||
#define HMBOUND_LOCK BIT0
|
||||
#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A
|
||||
#define HLEGACY_SMI_PIN_VALUE BIT12
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69
|
||||
|
||||
//
|
||||
// System On Chip Unit (SOCUnit) Registers.
|
||||
//
|
||||
#define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00
|
||||
#define B_STPDDRCFG_FORCE_RECOVERY BIT0
|
||||
#define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25
|
||||
#define B_ROM_FUSE_IN_SECURE_SKU BIT6
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31
|
||||
#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)
|
||||
#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3
|
||||
#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
|
||||
#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8
|
||||
#define B_TSCGF1_CONFIG_IBGEN BIT17
|
||||
#define B_TSCGF1_CONFIG_IBGEN_BP 17
|
||||
#define B_TSCGF1_CONFIG_IBGCHOPEN BIT18
|
||||
#define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18
|
||||
#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14
|
||||
#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32
|
||||
#define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF
|
||||
#define B_TSCGF2_CONFIG_IDSCONTROL_BP 0
|
||||
#define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000
|
||||
#define B_TSCGF2_CONFIG_IDSTIMING_BP 16
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33
|
||||
#define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000
|
||||
#define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24
|
||||
#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8)
|
||||
#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8
|
||||
#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF
|
||||
#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34
|
||||
#define B_TSCGF3_CONFIG_ITSRST BIT0
|
||||
#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11
|
||||
#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36
|
||||
#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20
|
||||
#define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19
|
||||
#define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18
|
||||
#define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17
|
||||
#define SOCCLKEN_CONFIG_BB_RST_B BIT16
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51
|
||||
#define B_CFG_STICKY_RW_SMM_VIOLATION BIT0
|
||||
#define B_CFG_STICKY_RW_HMB_VIOLATION BIT1
|
||||
#define B_CFG_STICKY_RW_IMR_VIOLATION BIT2
|
||||
#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3
|
||||
#define B_CFG_STICKY_RW_WARM_RST BIT4
|
||||
#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9
|
||||
#define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION)
|
||||
#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST)
|
||||
|
||||
//
|
||||
// iCLK Registers.
|
||||
//
|
||||
#define QUARK_ICLK_MUXTOP 0x0140
|
||||
#define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23)
|
||||
#define B_MUXTOP_FLEX2_BP 23
|
||||
#define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20)
|
||||
#define B_MUXTOP_FLEX1_BP 20
|
||||
|
||||
#define QUARK_ICLK_SSC1 0x0314
|
||||
#define QUARK_ICLK_SSC2 0x0414
|
||||
#define QUARK_ICLK_SSC3 0x0514
|
||||
#define QUARK_ICLK_REF2_DBUFF0 0x2000
|
||||
|
||||
//
|
||||
// PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID).
|
||||
//
|
||||
#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080
|
||||
#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180
|
||||
#define OCFGPIMIXLOAD_1_0 BIT6
|
||||
#define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F
|
||||
|
||||
//
|
||||
// QNC ICH Equates
|
||||
//
|
||||
#define V_INTEL_VENDOR_ID 0x8086
|
||||
|
||||
#define PCI_BUS_NUMBER_QNC 0x00
|
||||
|
||||
//
|
||||
// PCI to LPC Bridge Registers (D31:F0)
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_QNC_LPC 31
|
||||
#define PCI_FUNCTION_NUMBER_QNC_LPC 0
|
||||
|
||||
#define R_QNC_LPC_VENDOR_ID 0x00
|
||||
#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID
|
||||
#define R_QNC_LPC_DEVICE_ID 0x02
|
||||
#define QUARK_V_LPC_DEVICE_ID_0 0x095E
|
||||
#define R_QNC_LPC_REV_ID 0x08
|
||||
|
||||
#define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43
|
||||
#define B_QNC_LPC_SMBUS_BASE_EN (BIT31)
|
||||
#define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6]
|
||||
//
|
||||
// SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h)
|
||||
// Suggested Value for SMBA = 0x1040
|
||||
//
|
||||
#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W
|
||||
#define B_QNC_SMBUS_START (BIT4) // Start/Stop
|
||||
#define V_QNC_SMBUS_HCTL_CMD_QUICK 0
|
||||
#define V_QNC_SMBUS_HCTL_CMD_BYTE 1
|
||||
#define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2
|
||||
#define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3
|
||||
#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4
|
||||
#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5
|
||||
|
||||
#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W
|
||||
#define B_QNC_SMBUS_BERR (BIT2) // BUS Error
|
||||
#define B_QNC_SMBUS_DERR (BIT1) // Device Error
|
||||
#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status
|
||||
#define B_QNC_SMBUS_HSTS_ALL 0x07
|
||||
|
||||
#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W
|
||||
#define V_QNC_SMBUS_HCLK_100KHZ 0x0054
|
||||
|
||||
#define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W
|
||||
#define V_QNC_SMBUS_RW_SEL_READ 1
|
||||
#define V_QNC_SMBUS_RW_SEL_WRITE 0
|
||||
|
||||
#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W
|
||||
#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W
|
||||
#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W
|
||||
#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh
|
||||
|
||||
#define R_QNC_LPC_GBA_BASE 0x44
|
||||
#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0
|
||||
//
|
||||
// GPIO register offsets from GBA - "GPIO" (D31:F0:R44h)
|
||||
// Suggested Value for GBA = 0x1080
|
||||
//
|
||||
#define R_QNC_GPIO_CGEN_CORE_WELL 0x00
|
||||
#define R_QNC_GPIO_CGIO_CORE_WELL 0x04
|
||||
#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08
|
||||
#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable
|
||||
#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable
|
||||
#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable
|
||||
#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable
|
||||
#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status
|
||||
#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20
|
||||
#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24
|
||||
#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28
|
||||
#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable
|
||||
#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable
|
||||
#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable
|
||||
#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable
|
||||
#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status
|
||||
#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable
|
||||
#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable
|
||||
|
||||
#define R_QNC_LPC_PM1BLK 0x48
|
||||
#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0
|
||||
//
|
||||
// ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h)
|
||||
// Suggested Value for PM1BLK = 0x1000
|
||||
//
|
||||
#define R_QNC_PM1BLK_PM1S 0x00
|
||||
#define S_QNC_PM1BLK_PM1S 2
|
||||
#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)
|
||||
#define B_QNC_PM1BLK_PM1S_WAKE (BIT15)
|
||||
#define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14)
|
||||
#define B_QNC_PM1BLK_PM1S_RTC (BIT10)
|
||||
#define B_QNC_PM1BLK_PM1S_GLOB (BIT5)
|
||||
#define B_QNC_PM1BLK_PM1S_TO (BIT0)
|
||||
#define N_QNC_PM1BLK_PM1S_RTC 10
|
||||
|
||||
|
||||
#define R_QNC_PM1BLK_PM1E 0x02
|
||||
#define S_QNC_PM1BLK_PM1E 2
|
||||
#define B_QNC_PM1BLK_PM1E_PWAKED (BIT14)
|
||||
#define B_QNC_PM1BLK_PM1E_RTC (BIT10)
|
||||
#define B_QNC_PM1BLK_PM1E_GLOB (BIT5)
|
||||
#define N_QNC_PM1BLK_PM1E_RTC 10
|
||||
|
||||
#define R_QNC_PM1BLK_PM1C 0x04
|
||||
#define B_QNC_PM1BLK_PM1C_SLPEN (BIT13)
|
||||
#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10)
|
||||
#define V_S0 0x00000000
|
||||
#define V_S3 0x00001400
|
||||
#define V_S4 0x00001800
|
||||
#define V_S5 0x00001C00
|
||||
#define B_QNC_PM1BLK_PM1C_SCIEN (BIT0)
|
||||
|
||||
#define R_QNC_PM1BLK_PM1T 0x08
|
||||
|
||||
#define R_QNC_LPC_GPE0BLK 0x4C
|
||||
#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0
|
||||
// Suggested Value for GPE0BLK = 0x10C0
|
||||
//
|
||||
#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status
|
||||
#define S_QNC_GPE0BLK_GPE0S 4
|
||||
#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg
|
||||
#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE
|
||||
#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO
|
||||
#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE
|
||||
#define N_QNC_GPE0BLK_GPE0S_THRM 12
|
||||
|
||||
#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable
|
||||
#define S_QNC_GPE0BLK_GPE0E 4
|
||||
#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE
|
||||
#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO
|
||||
#define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE
|
||||
#define N_QNC_GPE0BLK_GPE0E_THRM 12
|
||||
|
||||
#define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable
|
||||
#define S_QNC_GPE0BLK_SMIE 4
|
||||
#define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F
|
||||
#define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM
|
||||
#define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep
|
||||
#define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer
|
||||
#define N_QNC_GPE0BLK_SMIE_GPIO 9
|
||||
#define N_QNC_GPE0BLK_SMIE_ESMI 8
|
||||
#define N_QNC_GPE0BLK_SMIE_APM 4
|
||||
#define N_QNC_GPE0BLK_SMIE_SPI 3
|
||||
#define N_QNC_GPE0BLK_SMIE_SLP 2
|
||||
#define N_QNC_GPE0BLK_SMIE_SWT 1
|
||||
|
||||
#define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register.
|
||||
#define S_QNC_GPE0BLK_SMIS 4
|
||||
#define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F
|
||||
#define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI
|
||||
#define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM
|
||||
#define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI
|
||||
#define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep
|
||||
#define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer
|
||||
#define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS
|
||||
#define N_QNC_GPE0BLK_SMIS_GPIO 9
|
||||
#define N_QNC_GPE0BLK_SMIS_APM 4
|
||||
#define N_QNC_GPE0BLK_SMIS_SPI 3
|
||||
#define N_QNC_GPE0BLK_SMIS_SLP 2
|
||||
#define N_QNC_GPE0BLK_SMIS_SWT 1
|
||||
|
||||
#define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well
|
||||
#define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable
|
||||
|
||||
#define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well
|
||||
#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad
|
||||
|
||||
#define R_QNC_LPC_ACTL 0x58
|
||||
#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00
|
||||
|
||||
//
|
||||
// Number of PIRQs supported. PIRQA~PIRQH
|
||||
//
|
||||
#define QNC_NUMBER_PIRQS 8
|
||||
#define R_QNC_LPC_PIRQA_ROUT 0x60
|
||||
#define R_QNC_LPC_PIRQB_ROUT 0x61
|
||||
#define R_QNC_LPC_PIRQC_ROUT 0x62
|
||||
#define R_QNC_LPC_PIRQD_ROUT 0x63
|
||||
#define R_QNC_LPC_PIRQE_ROUT 0x64
|
||||
#define R_QNC_LPC_PIRQF_ROUT 0x65
|
||||
#define R_QNC_LPC_PIRQG_ROUT 0x66
|
||||
#define R_QNC_LPC_PIRQH_ROUT 0x67
|
||||
|
||||
//
|
||||
// Bit values are the same for R_TNC_LPC_PIRQA_ROUT to
|
||||
// R_TNC_LPC_PIRQH_ROUT
|
||||
#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)
|
||||
|
||||
#define R_QNC_LPC_WDTBA 0x84
|
||||
// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN
|
||||
#define R_QNC_LPC_WDT_WDTCR 0x10
|
||||
#define R_QNC_LPC_WDT_WDTLR 0x18
|
||||
// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END
|
||||
|
||||
#define R_QNC_LPC_FWH_BIOS_DEC 0xD4
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24)
|
||||
|
||||
#define R_QNC_LPC_BIOS_CNTL 0xD8
|
||||
#define S_QNC_LPC_BIOS_CNTL 4
|
||||
#define B_QNC_LPC_BIOS_CNTL_PFE (BIT8)
|
||||
#define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5)
|
||||
#define B_QNC_LPC_BIOS_CNTL_BCD (BIT2)
|
||||
#define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)
|
||||
#define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0)
|
||||
#define N_QNC_LPC_BIOS_CNTL_BLE 1
|
||||
#define N_QNC_LPC_BIOS_CNTL_BIOSWE 0
|
||||
|
||||
#define R_QNC_LPC_RCBA 0xF0
|
||||
#define B_QNC_LPC_RCBA_MASK 0xFFFFC000
|
||||
#define B_QNC_LPC_RCBA_EN (BIT0)
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Fixed IO Decode on QuarkNcSocId
|
||||
//
|
||||
// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master
|
||||
// 40h(3B): R/W 8254
|
||||
// 43h(1B): W 8254
|
||||
// 50h(3B): R/W 8254
|
||||
// 53h(1B): W 8254
|
||||
// 61h(1B): R/W NMI Controller
|
||||
// 63h(1B): R/W NMI Controller - can be disabled
|
||||
// 65h(1B): R/W NMI Controller - can be disabled
|
||||
// 67h(1B): R/W NMI Controller - can be disabled
|
||||
// 70h(1B): W NMI & RTC
|
||||
// 71h(1B): R/W RTC
|
||||
// 72h(1B): R RTC; W NMI&RTC
|
||||
// 73h(1B): R/W RTC
|
||||
// 74h(1B): R RTC; W NMI&RTC
|
||||
// 75h(1B): R/W RTC
|
||||
// 76h(1B): R RTC; W NMI&RTC
|
||||
// 77h(1B): R/W RTC
|
||||
// 84h(3B): R/W Internal/LPC
|
||||
// 88h(1B): R/W Internal/LPC
|
||||
// 8Ch(3B): R/W Internal/LPC
|
||||
// A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave
|
||||
// B2h(1B) B3h(1B): R/W Power management
|
||||
// 3B0h-3BBh: R/W VGA
|
||||
// 3C0h-3DFh: R/W VGA
|
||||
// CF8h(4B): R/W Internal
|
||||
// CF9h(1B): R/W LPC
|
||||
// CFCh(4B): R/W Internal
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define R_APM_CNT 0xB2
|
||||
|
||||
//
|
||||
// Reset Generator I/O Port
|
||||
//
|
||||
#define RST_CNT 0xCF9
|
||||
#define B_RST_CNT_COLD_RST (BIT3) // Cold reset
|
||||
#define B_RST_CNT_WARM_RST (BIT1) // Warm reset
|
||||
|
||||
//
|
||||
// Processor interface registers (NMI)
|
||||
//
|
||||
|
||||
#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20
|
||||
#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21
|
||||
#define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0
|
||||
|
||||
//
|
||||
// Pci Express Root Ports (D23:F0/F1)
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23
|
||||
#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0
|
||||
#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1
|
||||
|
||||
#define MAX_PCI_EXPRESS_ROOT_PORTS 2
|
||||
|
||||
#define R_QNC_PCIE_BNUM 0x18
|
||||
#define R_QNC_PCIE_CAP_PTR 0x34
|
||||
|
||||
#define PCIE_CAPID 0x10 //PCIE Capability ID
|
||||
#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID
|
||||
#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset
|
||||
#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset
|
||||
#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset
|
||||
#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset
|
||||
#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset
|
||||
|
||||
#define R_QNC_PCIE_XCAP 0x42 //~ 43h
|
||||
#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented
|
||||
#define R_QNC_PCIE_DCAP 0x44 //~ 47h
|
||||
#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency
|
||||
#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency
|
||||
#define R_QNC_PCIE_DCTL 0x48 //~ 49h
|
||||
#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable
|
||||
#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable
|
||||
#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable
|
||||
#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable
|
||||
#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh
|
||||
#define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported
|
||||
#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask
|
||||
#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask
|
||||
#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask
|
||||
#define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask
|
||||
#define R_QNC_PCIE_LCTL 0x50 //~ 51h
|
||||
#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration
|
||||
#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link
|
||||
#define R_QNC_PCIE_LSTS 0x52 //~ 53h
|
||||
#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration
|
||||
#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training
|
||||
#define R_QNC_PCIE_SLCAP 0x54 //~ 57h
|
||||
#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F
|
||||
#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7]
|
||||
#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7]
|
||||
#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19]
|
||||
#define R_QNC_PCIE_SLCTL 0x58 //~ 59h
|
||||
#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable
|
||||
#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable
|
||||
#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable
|
||||
#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh
|
||||
#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected
|
||||
#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed
|
||||
#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed
|
||||
#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh
|
||||
#define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable
|
||||
#define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable
|
||||
#define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable
|
||||
#define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable
|
||||
#define R_QNC_PCIE_SVID 0x94 //~ 97h
|
||||
#define R_QNC_PCIE_CCFG 0xD0 //~ D3h
|
||||
#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable
|
||||
#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size
|
||||
#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size
|
||||
#define R_QNC_PCIE_MPC2 0xD4 //~ D7h
|
||||
#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode
|
||||
#define R_QNC_PCIE_MPC 0xD8 //~ DBh
|
||||
#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable
|
||||
#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable
|
||||
|
||||
#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable
|
||||
#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable
|
||||
#define R_QNC_PCIE_IOSFSBCTL 0xF6
|
||||
#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter.
|
||||
#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE.
|
||||
|
||||
#define V_PCIE_MAX_TRY_TIMES 200
|
||||
|
||||
//
|
||||
// Misc PCI register offsets and sizes
|
||||
//
|
||||
#define R_EFI_PCI_SVID 0x2C
|
||||
|
||||
//
|
||||
// IO_APIC
|
||||
//
|
||||
#define IOAPIC_BASE 0xFEC00000
|
||||
#define IOAPIC_SIZE 0x1000
|
||||
|
||||
//
|
||||
// Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h)
|
||||
// Suggested Value for RCBA = 0xFED1C000
|
||||
//
|
||||
|
||||
#define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB
|
||||
#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status
|
||||
#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown
|
||||
#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status
|
||||
#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status
|
||||
#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress
|
||||
|
||||
#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control
|
||||
#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable
|
||||
#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64)
|
||||
#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer
|
||||
#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer
|
||||
#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence
|
||||
#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go
|
||||
|
||||
#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address
|
||||
#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask
|
||||
#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0
|
||||
#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration
|
||||
#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration
|
||||
#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0
|
||||
#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)
|
||||
#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)
|
||||
#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1)
|
||||
#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU
|
||||
|
||||
#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0.
|
||||
#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1.
|
||||
#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2.
|
||||
#define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers.
|
||||
|
||||
#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route
|
||||
#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route
|
||||
#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route
|
||||
#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user