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QuarkSocPkg: Add new package for Quark SoC X1000

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Changes for V4
==============
1) Remove Unicode character from C source file
2) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
   from QuarkPlatformPkg commit to QuarkSocPkg commit

Changes for V2
==============
1) Sync with new APIs in SmmCpuFeaturesLib class
2) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
3) Remove PCI serial driver from QuarkSocPkg
4) Apply optimizations to MtrrLib from MtrrLib in UefiCpuPkg
5) Convert all UNI files to utf-8
6) Replace tabs with spaces and remove trailing spaces
7) Add License.txt

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19286 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2015-12-15 19:22:23 +00:00
committed by mdkinney
parent 46ff196fde
commit 9b6bbcdbfd
176 changed files with 54761 additions and 0 deletions
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290
QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h Normal file
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/** @file
Library that provides QNC specific library services in PEI phase
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __INTEL_QNC_LIB_H__
#define __INTEL_QNC_LIB_H__
/**
This function initializes the QNC register before MRC.
It sets RCBA, PMBASE, disable Watchdog timer and initialize QNC GPIO.
If the function cannot complete it'll ASSERT().
**/
VOID
EFIAPI
PeiQNCPreMemInit (
VOID
);
/**
Used to check SCH if it's S3 state. Clear the register state after query.
@retval TRUE if it's S3 state.
@retval FALSE if it's not S3 state.
**/
BOOLEAN
EFIAPI
QNCCheckS3AndClearState (
VOID
);
/**
Used to check SCH if system wakes up from power on reset. Clear the register state after query.
@retval TRUE if system wakes up from power on reset
@retval FALSE if system does not wake up from power on reset
**/
BOOLEAN
EFIAPI
QNCCheckPowerOnResetAndClearState (
VOID
);
/**
This function is used to clear SMI and wake status.
**/
VOID
EFIAPI
QNCClearSmiAndWake (
VOID
);
/**
Used to initialize the QNC register after MRC.
**/
VOID
EFIAPI
PeiQNCPostMemInit (
VOID
);
/** Send DRAM Ready opcode.
@param[in] OpcodeParam Parameter to DRAM ready opcode.
@retval VOID
**/
VOID
EFIAPI
QNCSendOpcodeDramReady (
IN UINT32 OpcodeParam
);
/**
Relocate RMU Main binary to memory after MRC to improve performance.
@param[in] DestBaseAddress - Specify the new memory address for the RMU Main binary.
@param[in] SrcBaseAddress - Specify the current memory address for the RMU Main binary.
@param[in] Size - Specify size of the RMU Main binary.
@retval VOID
**/
VOID
EFIAPI
RmuMainRelocation (
IN CONST UINT32 DestBaseAddress,
IN CONST UINT32 SrcBaseAddress,
IN CONST UINTN Size
);
/**
Get the total memory size
**/
UINT32
EFIAPI
QNCGetTotalMemorysize (
VOID
);
/**
Get the memory range of TSEG.
The TSEG's memory is below TOLM.
@param[out] BaseAddress The base address of TSEG's memory range
@param[out] MemorySize The size of TSEG's memory range
**/
VOID
EFIAPI
QNCGetTSEGMemoryRange (
OUT UINT64 *BaseAddress,
OUT UINT64 *MemorySize
);
/**
Updates the PAM registers in the MCH for the requested range and mode.
@param Start The start address of the memory region
@param Length The length, in bytes, of the memory region
@param ReadEnable Pointer to the boolean variable on whether to enable read for legacy memory section.
If NULL, then read attribute will not be touched by this call.
@param ReadEnable Pointer to the boolean variable on whether to enable write for legacy memory section.
If NULL, then write attribute will not be touched by this call.
@param Granularity A pointer to granularity, in bytes, that the PAM registers support
@retval RETURN_SUCCESS The PAM registers in the MCH were updated
@retval RETURN_INVALID_PARAMETER The memory range is not valid in legacy region.
**/
RETURN_STATUS
EFIAPI
QNCLegacyRegionManipulation (
IN UINT32 Start,
IN UINT32 Length,
IN BOOLEAN *ReadEnable,
IN BOOLEAN *WriteEnable,
OUT UINT32 *Granularity
);
/**
Do early init of pci express rootports on Soc.
**/
VOID
EFIAPI
PciExpressEarlyInit (
VOID
);
/**
Complete initialization of all the pci express rootports on Soc.
**/
EFI_STATUS
EFIAPI
PciExpressInit (
);
/**
Determine if QNC is supported.
@retval FALSE QNC is not supported.
@retval TRUE QNC is supported.
**/
BOOLEAN
EFIAPI
IsQncSupported (
VOID
);
/**
Get the DeviceId of the SoC
@retval PCI DeviceId of the SoC
**/
UINT16
EFIAPI
QncGetSocDeviceId (
VOID
);
/**
Enable SMI detection of legacy flash access violations.
**/
VOID
EFIAPI
QncEnableLegacyFlashAccessViolationSmi (
VOID
);
/**
Setup RMU Thermal sensor registers for Vref mode.
**/
VOID
EFIAPI
QNCThermalSensorSetVRefMode (
VOID
);
/**
Setup RMU Thermal sensor registers for Ratiometric mode.
**/
VOID
EFIAPI
QNCThermalSensorSetRatiometricMode (
VOID
);
/**
Setup RMU Thermal sensor trip point values.
@param[in] CatastrophicTripOnDegreesCelsius - Catastrophic set trip point threshold.
@param[in] HotTripOnDegreesCelsius - Hot set trip point threshold.
@param[in] HotTripOffDegreesCelsius - Hot clear trip point threshold.
@retval VOID
**/
EFI_STATUS
EFIAPI
QNCThermalSensorSetTripValues (
IN CONST UINTN CatastrophicTripOnDegreesCelsius,
IN CONST UINTN HotTripOnDegreesCelsius,
IN CONST UINTN HotTripOffDegreesCelsius
);
/**
Enable RMU Thermal sensor with a Catastrophic Trip point.
@retval EFI_SUCCESS Trip points setup.
@retval EFI_INVALID_PARAMETER Invalid trip point value.
**/
EFI_STATUS
EFIAPI
QNCThermalSensorEnableWithCatastrophicTrip (
IN CONST UINTN CatastrophicTripOnDegreesCelsius
);
/**
Lock all RMU Thermal sensor control & trip point registers.
**/
VOID
EFIAPI
QNCThermalSensorLockAllRegisters (
VOID
);
/**
Set chipset policy for double bit ECC error.
@param[in] PolicyValue Policy to config on double bit ECC error.
**/
VOID
EFIAPI
QNCPolicyDblEccBitErr (
IN CONST UINT32 PolicyValue
);
/**
Determine if running on secure Quark hardware Sku.
@retval FALSE Base Quark Sku or unprovisioned Secure Sku running.
@retval TRUE Provisioned SecureSku hardware running.
**/
BOOLEAN
EFIAPI
QncIsSecureProvisionedSku (
VOID
);
#endif

167
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h Normal file
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/** @file
Library functions for Setting QNC internal network port
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __QNC_ACCESS_LIB_H__
#define __QNC_ACCESS_LIB_H__
#include <IntelQNCRegs.h>
#define MESSAGE_READ_DW(Port, Reg) \
(UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
#define MESSAGE_WRITE_DW(Port, Reg) \
(UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
#define ALT_MESSAGE_READ_DW(Port, Reg) \
(UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
#define ALT_MESSAGE_WRITE_DW(Port, Reg) \
(UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
#define MESSAGE_IO_READ_DW(Port, Reg) \
(UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
#define MESSAGE_IO_WRITE_DW(Port, Reg) \
(UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
#define MESSAGE_SHADOW_DW(Port, Reg) \
(UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
/**
Read required data from QNC internal message network
**/
UINT32
EFIAPI
QNCPortRead(
UINT8 Port,
UINT32 RegAddress
);
/**
Write prepared data into QNC internal message network.
**/
VOID
EFIAPI
QNCPortWrite (
UINT8 Port,
UINT32 RegAddress,
UINT32 WriteValue
);
/**
Read required data from QNC internal message network
**/
UINT32
EFIAPI
QNCAltPortRead(
UINT8 Port,
UINT32 RegAddress
);
/**
Write prepared data into QNC internal message network.
**/
VOID
EFIAPI
QNCAltPortWrite (
UINT8 Port,
UINT32 RegAddress,
UINT32 WriteValue
);
/**
Read required data from QNC internal message network
**/
UINT32
EFIAPI
QNCPortIORead(
UINT8 Port,
UINT32 RegAddress
);
/**
Write prepared data into QNC internal message network.
**/
VOID
EFIAPI
QNCPortIOWrite (
UINT8 Port,
UINT32 RegAddress,
UINT32 WriteValue
);
/**
This is for the special consideration for QNC MMIO write, as required by FWG,
a reading must be performed after MMIO writing to ensure the expected write
is processed and data is flushed into chipset
**/
RETURN_STATUS
EFIAPI
QNCMmIoWrite (
UINT32 MmIoAddress,
QNC_MEM_IO_WIDTH Width,
UINT32 DataNumber,
VOID *pData
);
UINT32
EFIAPI
QncHsmmcRead (
VOID
);
VOID
EFIAPI
QncHsmmcWrite (
UINT32 WriteValue
);
VOID
EFIAPI
QncImrWrite (
UINT32 ImrBaseOffset,
UINT32 ImrLow,
UINT32 ImrHigh,
UINT32 ImrReadMask,
UINT32 ImrWriteMask
);
VOID
EFIAPI
QncIClkAndThenOr (
UINT32 RegAddress,
UINT32 AndValue,
UINT32 OrValue
);
VOID
EFIAPI
QncIClkOr (
UINT32 RegAddress,
UINT32 OrValue
);
UINTN
EFIAPI
QncGetPciExpressBaseAddress (
VOID
);
#endif

63
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h Normal file
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/** @file
QNC Smm Library Services header file.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __QNC_SMM_LIB_H__
#define __QNC_SMM_LIB_H__
/**
This routine is the chipset code that accepts a request to "open" a region of SMRAM.
The region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
The use of "open" means that the memory is visible from all boot-service
and SMM agents.
@retval FALSE Cannot open a locked SMRAM region
@retval TRUE Success to open SMRAM region.
**/
BOOLEAN
EFIAPI
QNCOpenSmramRegion (
VOID
);
/**
This routine is the chipset code that accepts a request to "close" a region of SMRAM.
The region could be legacy AB or TSEG near top of physical memory.
The use of "close" means that the memory is only visible from SMM agents,
not from BS or RT code.
@retval FALSE Cannot open a locked SMRAM region
@retval TRUE Success to open SMRAM region.
**/
BOOLEAN
EFIAPI
QNCCloseSmramRegion (
VOID
);
/**
This routine is the chipset code that accepts a request to "lock" SMRAM.
The region could be legacy AB or TSEG near top of physical memory.
The use of "lock" means that the memory can no longer be opened
to BS state.
**/
VOID
EFIAPI
QNCLockSmramRegion (
VOID
);
#endif