QuarkSocPkg: Add new package for Quark SoC X1000
Changes for V4 ============== 1) Remove Unicode character from C source file 2) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode from QuarkPlatformPkg commit to QuarkSocPkg commit Changes for V2 ============== 1) Sync with new APIs in SmmCpuFeaturesLib class 2) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg 3) Remove PCI serial driver from QuarkSocPkg 4) Apply optimizations to MtrrLib from MtrrLib in UefiCpuPkg 5) Convert all UNI files to utf-8 6) Replace tabs with spaces and remove trailing spaces 7) Add License.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19286 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
290
QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
Normal file
290
QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
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@@ -0,0 +1,290 @@
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/** @file
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Library that provides QNC specific library services in PEI phase
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __INTEL_QNC_LIB_H__
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#define __INTEL_QNC_LIB_H__
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/**
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This function initializes the QNC register before MRC.
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It sets RCBA, PMBASE, disable Watchdog timer and initialize QNC GPIO.
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If the function cannot complete it'll ASSERT().
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**/
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VOID
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EFIAPI
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PeiQNCPreMemInit (
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VOID
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);
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/**
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Used to check SCH if it's S3 state. Clear the register state after query.
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@retval TRUE if it's S3 state.
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@retval FALSE if it's not S3 state.
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**/
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BOOLEAN
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EFIAPI
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QNCCheckS3AndClearState (
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VOID
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);
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/**
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Used to check SCH if system wakes up from power on reset. Clear the register state after query.
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@retval TRUE if system wakes up from power on reset
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@retval FALSE if system does not wake up from power on reset
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**/
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BOOLEAN
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EFIAPI
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QNCCheckPowerOnResetAndClearState (
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VOID
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);
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/**
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This function is used to clear SMI and wake status.
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**/
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VOID
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EFIAPI
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QNCClearSmiAndWake (
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VOID
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);
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/**
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Used to initialize the QNC register after MRC.
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**/
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VOID
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EFIAPI
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PeiQNCPostMemInit (
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VOID
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);
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/** Send DRAM Ready opcode.
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@param[in] OpcodeParam Parameter to DRAM ready opcode.
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@retval VOID
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**/
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VOID
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EFIAPI
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QNCSendOpcodeDramReady (
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IN UINT32 OpcodeParam
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);
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/**
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Relocate RMU Main binary to memory after MRC to improve performance.
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@param[in] DestBaseAddress - Specify the new memory address for the RMU Main binary.
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@param[in] SrcBaseAddress - Specify the current memory address for the RMU Main binary.
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@param[in] Size - Specify size of the RMU Main binary.
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@retval VOID
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**/
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VOID
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EFIAPI
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RmuMainRelocation (
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IN CONST UINT32 DestBaseAddress,
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IN CONST UINT32 SrcBaseAddress,
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IN CONST UINTN Size
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);
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/**
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Get the total memory size
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**/
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UINT32
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EFIAPI
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QNCGetTotalMemorysize (
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VOID
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);
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/**
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Get the memory range of TSEG.
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The TSEG's memory is below TOLM.
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@param[out] BaseAddress The base address of TSEG's memory range
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@param[out] MemorySize The size of TSEG's memory range
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**/
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VOID
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EFIAPI
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QNCGetTSEGMemoryRange (
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OUT UINT64 *BaseAddress,
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OUT UINT64 *MemorySize
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);
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/**
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Updates the PAM registers in the MCH for the requested range and mode.
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@param Start The start address of the memory region
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@param Length The length, in bytes, of the memory region
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@param ReadEnable Pointer to the boolean variable on whether to enable read for legacy memory section.
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If NULL, then read attribute will not be touched by this call.
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@param ReadEnable Pointer to the boolean variable on whether to enable write for legacy memory section.
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If NULL, then write attribute will not be touched by this call.
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@param Granularity A pointer to granularity, in bytes, that the PAM registers support
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@retval RETURN_SUCCESS The PAM registers in the MCH were updated
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@retval RETURN_INVALID_PARAMETER The memory range is not valid in legacy region.
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**/
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RETURN_STATUS
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EFIAPI
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QNCLegacyRegionManipulation (
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IN UINT32 Start,
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IN UINT32 Length,
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IN BOOLEAN *ReadEnable,
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IN BOOLEAN *WriteEnable,
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OUT UINT32 *Granularity
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);
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/**
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Do early init of pci express rootports on Soc.
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**/
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VOID
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EFIAPI
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PciExpressEarlyInit (
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VOID
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);
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/**
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Complete initialization of all the pci express rootports on Soc.
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**/
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EFI_STATUS
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EFIAPI
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PciExpressInit (
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);
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/**
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Determine if QNC is supported.
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@retval FALSE QNC is not supported.
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@retval TRUE QNC is supported.
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**/
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BOOLEAN
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EFIAPI
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IsQncSupported (
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VOID
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);
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/**
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Get the DeviceId of the SoC
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@retval PCI DeviceId of the SoC
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**/
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UINT16
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EFIAPI
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QncGetSocDeviceId (
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VOID
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);
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/**
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Enable SMI detection of legacy flash access violations.
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**/
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VOID
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EFIAPI
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QncEnableLegacyFlashAccessViolationSmi (
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VOID
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);
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/**
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Setup RMU Thermal sensor registers for Vref mode.
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**/
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VOID
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EFIAPI
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QNCThermalSensorSetVRefMode (
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VOID
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);
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/**
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Setup RMU Thermal sensor registers for Ratiometric mode.
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**/
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VOID
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EFIAPI
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QNCThermalSensorSetRatiometricMode (
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VOID
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);
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/**
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Setup RMU Thermal sensor trip point values.
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@param[in] CatastrophicTripOnDegreesCelsius - Catastrophic set trip point threshold.
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@param[in] HotTripOnDegreesCelsius - Hot set trip point threshold.
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@param[in] HotTripOffDegreesCelsius - Hot clear trip point threshold.
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@retval VOID
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**/
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EFI_STATUS
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EFIAPI
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QNCThermalSensorSetTripValues (
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IN CONST UINTN CatastrophicTripOnDegreesCelsius,
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IN CONST UINTN HotTripOnDegreesCelsius,
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IN CONST UINTN HotTripOffDegreesCelsius
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);
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/**
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Enable RMU Thermal sensor with a Catastrophic Trip point.
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@retval EFI_SUCCESS Trip points setup.
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@retval EFI_INVALID_PARAMETER Invalid trip point value.
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**/
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EFI_STATUS
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EFIAPI
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QNCThermalSensorEnableWithCatastrophicTrip (
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IN CONST UINTN CatastrophicTripOnDegreesCelsius
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);
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/**
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Lock all RMU Thermal sensor control & trip point registers.
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**/
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VOID
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EFIAPI
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QNCThermalSensorLockAllRegisters (
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VOID
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);
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/**
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Set chipset policy for double bit ECC error.
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@param[in] PolicyValue Policy to config on double bit ECC error.
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**/
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VOID
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EFIAPI
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QNCPolicyDblEccBitErr (
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IN CONST UINT32 PolicyValue
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);
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/**
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Determine if running on secure Quark hardware Sku.
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@retval FALSE Base Quark Sku or unprovisioned Secure Sku running.
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@retval TRUE Provisioned SecureSku hardware running.
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**/
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BOOLEAN
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EFIAPI
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QncIsSecureProvisionedSku (
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VOID
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);
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#endif
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167
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
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167
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
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@@ -0,0 +1,167 @@
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/** @file
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Library functions for Setting QNC internal network port
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __QNC_ACCESS_LIB_H__
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#define __QNC_ACCESS_LIB_H__
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#include <IntelQNCRegs.h>
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#define MESSAGE_READ_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_WRITE_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define ALT_MESSAGE_READ_DW(Port, Reg) \
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(UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define ALT_MESSAGE_WRITE_DW(Port, Reg) \
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(UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_IO_READ_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_IO_WRITE_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_SHADOW_DW(Port, Reg) \
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(UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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/**
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Read required data from QNC internal message network
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**/
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UINT32
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EFIAPI
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QNCPortRead(
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UINT8 Port,
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UINT32 RegAddress
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);
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/**
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Write prepared data into QNC internal message network.
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**/
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VOID
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EFIAPI
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QNCPortWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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);
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/**
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Read required data from QNC internal message network
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**/
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UINT32
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EFIAPI
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QNCAltPortRead(
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UINT8 Port,
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UINT32 RegAddress
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);
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/**
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Write prepared data into QNC internal message network.
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**/
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VOID
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EFIAPI
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QNCAltPortWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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);
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/**
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Read required data from QNC internal message network
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**/
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UINT32
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EFIAPI
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QNCPortIORead(
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UINT8 Port,
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UINT32 RegAddress
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);
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/**
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Write prepared data into QNC internal message network.
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**/
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VOID
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EFIAPI
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QNCPortIOWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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);
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/**
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This is for the special consideration for QNC MMIO write, as required by FWG,
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a reading must be performed after MMIO writing to ensure the expected write
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is processed and data is flushed into chipset
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**/
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RETURN_STATUS
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EFIAPI
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QNCMmIoWrite (
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UINT32 MmIoAddress,
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QNC_MEM_IO_WIDTH Width,
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UINT32 DataNumber,
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VOID *pData
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);
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UINT32
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EFIAPI
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QncHsmmcRead (
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VOID
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);
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VOID
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EFIAPI
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QncHsmmcWrite (
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UINT32 WriteValue
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);
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VOID
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EFIAPI
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QncImrWrite (
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UINT32 ImrBaseOffset,
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UINT32 ImrLow,
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UINT32 ImrHigh,
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UINT32 ImrReadMask,
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UINT32 ImrWriteMask
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);
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VOID
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EFIAPI
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QncIClkAndThenOr (
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UINT32 RegAddress,
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UINT32 AndValue,
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UINT32 OrValue
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);
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VOID
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EFIAPI
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QncIClkOr (
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UINT32 RegAddress,
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UINT32 OrValue
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);
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UINTN
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EFIAPI
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QncGetPciExpressBaseAddress (
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VOID
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);
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#endif
|
63
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
Normal file
63
QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
Normal file
@@ -0,0 +1,63 @@
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/** @file
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QNC Smm Library Services header file.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
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**/
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#ifndef __QNC_SMM_LIB_H__
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#define __QNC_SMM_LIB_H__
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/**
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This routine is the chipset code that accepts a request to "open" a region of SMRAM.
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The region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
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The use of "open" means that the memory is visible from all boot-service
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and SMM agents.
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@retval FALSE Cannot open a locked SMRAM region
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@retval TRUE Success to open SMRAM region.
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**/
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BOOLEAN
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EFIAPI
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QNCOpenSmramRegion (
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VOID
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);
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/**
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This routine is the chipset code that accepts a request to "close" a region of SMRAM.
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The region could be legacy AB or TSEG near top of physical memory.
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The use of "close" means that the memory is only visible from SMM agents,
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not from BS or RT code.
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@retval FALSE Cannot open a locked SMRAM region
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@retval TRUE Success to open SMRAM region.
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**/
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BOOLEAN
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EFIAPI
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QNCCloseSmramRegion (
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VOID
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);
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/**
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This routine is the chipset code that accepts a request to "lock" SMRAM.
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The region could be legacy AB or TSEG near top of physical memory.
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The use of "lock" means that the memory can no longer be opened
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to BS state.
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**/
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VOID
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EFIAPI
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QNCLockSmramRegion (
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VOID
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);
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#endif
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|
Reference in New Issue
Block a user