sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

QuarkSocPkg: Add new package for Quark SoC X1000

Browse Source 
Changes for V4
==============
1) Remove Unicode character from C source file
2) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
   from QuarkPlatformPkg commit to QuarkSocPkg commit

Changes for V2
==============
1) Sync with new APIs in SmmCpuFeaturesLib class
2) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
3) Remove PCI serial driver from QuarkSocPkg
4) Apply optimizations to MtrrLib from MtrrLib in UefiCpuPkg
5) Convert all UNI files to utf-8
6) Replace tabs with spaces and remove trailing spaces
7) Add License.txt

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19286 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2015-12-15 19:22:23 +00:00
committed by mdkinney
parent 46ff196fde
commit 9b6bbcdbfd
176 changed files with 54761 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

120
QuarkSocPkg/QuarkSouthCluster/Include/CEATA.h Normal file
View File

@@ -0,0 +1,120 @@
/** @file
Header file for chipset CE-AT spec.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _CE_ATA_H
#define _CE_ATA_H
#pragma pack(1)
#define DATA_UNIT_SIZE 512
#define CMD60 60
#define CMD61 61
#define RW_MULTIPLE_REGISTER CMD60
#define RW_MULTIPLE_BLOCK CMD61
#define CE_ATA_SIG_CE 0xCE
#define CE_ATA_SIG_AA 0xAA
#define Reg_Features_Exp 01
#define Reg_SectorCount_Exp 02
#define Reg_LBALow_Exp 03
#define Reg_LBAMid_Exp 04
#define Reg_LBAHigh_Exp 05
#define Reg_Control 06
#define Reg_Features_Error 09
#define Reg_SectorCount 10
#define Reg_LBALow 11
#define Reg_LBAMid 12
#define Reg_LBAHigh 13
#define Reg_Device_Head 14
#define Reg_Command_Status 15
#define Reg_scrTempC 0x80
#define Reg_scrTempMaxP 0x84
#define Reg_scrTempMinP 0x88
#define Reg_scrStatus 0x8C
#define Reg_scrReallocsA 0x90
#define Reg_scrERetractsA 0x94
#define Reg_scrCapabilities 0x98
#define Reg_scrControl 0xC0
typedef struct {
UINT8 Reserved0;
UINT8 Features_Exp;
UINT8 SectorCount_Exp;
UINT8 LBALow_Exp;
UINT8 LBAMid_Exp;
UINT8 LBAHigh_Exp;
UINT8 Control;
UINT8 Reserved1[2];
UINT8 Features_Error;
UINT8 SectorCount;
UINT8 LBALow;
UINT8 LBAMid;
UINT8 LBAHigh;
UINT8 Device_Head;
UINT8 Command_Status;
}TASK_FILE;
//
//Reduced ATA command set
//
#define IDENTIFY_DEVICE 0xEC
#define READ_DMA_EXT 0x25
#define WRITE_DMA_EXT 0x35
#define STANDBY_IMMEDIATE 0xE0
#define FLUSH_CACHE_EXT 0xEA
typedef struct {
UINT16 Reserved0[10];
UINT16 SerialNumber[10];
UINT16 Reserved1[3];
UINT16 FirmwareRevision[4];
UINT16 ModelNumber[20];
UINT16 Reserved2[33];
UINT16 MajorVersion;
UINT16 Reserved3[19];
UINT16 MaximumLBA[4];
UINT16 Reserved4[2];
UINT16 Sectorsize;
UINT16 Reserved5;
UINT16 DeviceGUID[4];
UINT16 Reserved6[94];
UINT16 Features;
UINT16 MaxWritesPerAddress;
UINT16 Reserved7[47];
UINT16 IntegrityWord;
}IDENTIFY_DEVICE_DATA;
#pragma pack()
#endif

101
QuarkSocPkg/QuarkSouthCluster/Include/I2cRegs.h Normal file
View File

@@ -0,0 +1,101 @@
/** @file
Include file for I2C DXE Driver register definitions (PCIe config. space and memory space).
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _I2C_REGS_H_
#define _I2C_REGS_H_
//----------------------------------------------------------------------------
/// I2C Device Address
//----------------------------------------------------------------------------
typedef struct {
///
/// The I2C hardware address to which the I2C device is preassigned or allocated.
///
UINTN I2CDeviceAddress : 10;
} EFI_I2C_DEVICE_ADDRESS;
//----------------------------------------------------------------------------
/// I2C Addressing Mode (7-bit or 10 bit)
//----------------------------------------------------------------------------
typedef enum _EFI_I2C_ADDR_MODE {
EfiI2CSevenBitAddrMode,
EfiI2CTenBitAddrMode,
} EFI_I2C_ADDR_MODE;
//----------------------------------------------------------------------------
// I2C Controller B:D:F
//----------------------------------------------------------------------------
#define I2C_Bus 0x00
#define I2C_Device 0x15
#define I2C_Func 0x02
//----------------------------------------------------------------------------
// Memory Mapped Registers
//----------------------------------------------------------------------------
#define I2C_REG_CON 0x00 // Control Register
#define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10)
#define B_I2C_REG_CON_10BITADD_MASTER (BIT4) // 7-bit addressing (0) or 10-bit addressing (1)
#define I2C_REG_TAR 0x04 // Master Target Address Register
#define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
#define I2C_REG_DATA_CMD 0x10 // Data Buffer and Command Register
#define B_I2C_REG_DATA_CMD_RW (BIT8) // Data Buffer and Command Register Read/Write bit
#define B_I2C_REG_DATA_CMD_STOP (BIT9) // Data Buffer and Command Register STOP bit
#define B_I2C_REG_DATA_CMD_RESTART (BIT10) // Data Buffer and Command Register RESTART bit
#define I2C_REG_SS_SCL_HCNT 0x14 // Standard Speed Clock SCL High Count Register
#define I2C_REG_SS_SCL_LCNT 0x18 // Standard Speed Clock SCL Low Count Register
#define I2C_REG_FS_SCL_HCNT 0x1C // Fast Speed Clock SCL High Count Register
#define I2C_REG_FS_SCL_LCNT 0x20 // Fast Speed Clock SCL Low Count Register
#define I2C_REG_INTR_STAT 0x2C // Interrupt Status Register
#define B_I2C_REG_INTR_STAT_STOP_DET (BIT9) // Interrupt Status Register STOP_DET signal status
#define I2C_REG_INTR_MASK 0x30 // Interrupt Status Mask Register
#define I2C_REG_RAW_INTR_STAT 0x34 // Raw Interrupt Status Register
#define I2C_REG_RAW_INTR_STAT_STOP_DET (BIT9) // Raw Interrupt Status Register STOP_DET signal status.
#define I2C_REG_RAW_INTR_STAT_TX_ABRT (BIT6) // Raw Interrupt Status Register TX Abort status.
#define I2C_REG_RAW_INTR_STAT_TX_OVER (BIT3) // Raw Interrupt Status Register TX Overflow signal status.
#define I2C_REG_RAW_INTR_STAT_RX_OVER (BIT1) // Raw Interrupt Status Register RX Overflow signal status.
#define I2C_REG_RAW_INTR_STAT_RX_UNDER (BIT0) // Raw Interrupt Status Register RX Underflow signal status.
#define I2C_REG_RX_TL 0x38 // Receive FIFO Threshold Level Register
#define I2C_REG_TX_TL 0x3C // Transmit FIFO Threshold Level Register
#define I2C_REG_CLR_INT 0x40 // Clear Combined and Individual Interrupt Register
#define I2C_REG_CLR_RX_UNDER 0x44 // Clear RX Under Interrupt Register
#define I2C_REG_CLR_RX_OVER 0x48 // Clear RX Over Interrupt Register
#define I2C_REG_CLR_TX_OVER 0x4C // Clear TX Over Interrupt Register
#define I2C_REG_CLR_RD_REQ 0x50 // Clear RD REQ Interrupt Register
#define I2C_REG_CLR_TX_ABRT 0x54 // Clear TX ABRT Interrupt Register
#define I2C_REG_CLR_ACTIVITY 0x5C // Clear Activity Interrupt Register
#define I2C_REG_CLR_STOP_DET 0x60 // Clear STOP DET Interrupt Register
#define B_I2C_REG_CLR_STOP_DET (BIT0) // Clear STOP DET Interrupt Register
#define I2C_REG_CLR_START_DET 0x64 // Clear START DET Interrupt Register
#define B_I2C_REG_CLR_START_DET (BIT0) // Clear START DET Interrupt Register
#define I2C_REG_ENABLE 0x6C // Enable Register
#define B_I2C_REG_ENABLE (BIT0) // Enable (1) or disable (0) I2C Controller
#define I2C_REG_STATUS 0x70 // Status Register
#define I2C_REG_TXFLR 0x74 // Transmit FIFO Level Register
#define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register bits
#define I2C_REG_RXFLR 0x78 // Receive FIFO Level Register
#define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register bits
#define I2C_REG_SDA_HOLD 0x7C // SDA HOLD Register
#define I2C_REG_TX_ABRT_SOURCE 0x80 // Transmit Abort Source Register
#define I2C_REG_ENABLE_STATUS 0x9C // Enable Status Register
#define I2C_REG_FS_SPKLEN 0xA0 // SS and FS Spike Suppression Limit Register
//
// Features.
//
#define I2C_FIFO_SIZE 16
#endif

254
QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h Normal file
View File

@@ -0,0 +1,254 @@
/** @file
Header file for QuarkSCSocId Ioh.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IOH_H_
#define _IOH_H_
#ifndef BIT0
#define BIT0 0x01
#define BIT1 0x02
#define BIT2 0x04
#define BIT3 0x08
#define BIT4 0x10
#define BIT5 0x20
#define BIT6 0x40
#define BIT7 0x80
#define BIT8 0x100
#define BIT9 0x200
#define BIT00 0x00000001
#define BIT01 0x00000002
#define BIT02 0x00000004
#define BIT03 0x00000008
#define BIT04 0x00000010
#define BIT05 0x00000020
#define BIT06 0x00000040
#define BIT07 0x00000080
#define BIT08 0x00000100
#define BIT09 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#endif
#define IOH_PCI_CFG_ADDRESS(bus,dev,func,reg) \
((UINT32) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \
(((UINTN)func) << 8) + ((UINTN)reg) ))& 0x00000000ffffffff
//----------------------------------------------------------------------------
#define INTEL_VENDOR_ID 0x8086 // Intel Vendor ID
//----------------------------------------------------------------------------
// Pci Configuration Map Register Offsets
//----------------------------------------------------------------------------
#define PCI_REG_VID 0x00 // Vendor ID Register
#define PCI_REG_DID 0x02 // Device ID Register
#define PCI_REG_PCICMD 0x04 // PCI Command Register
#define PCI_REG_PCISTS 0x06 // PCI Status Register
#define PCI_REG_RID 0x08 // PCI Revision ID Register
#define PCI_REG_PI 0x09 // Programming Interface
#define PCI_REG_SCC 0x0a // Sub Class Code Register
#define PCI_REG_BCC 0x0b // Base Class Code Register
#define PCI_REG_PMLT 0x0d // Primary Master Latnecy Timer
#define PCI_REG_HDR 0x0e // Header Type Register
#define PCI_REG_PBUS 0x18 // Primary Bus Number Register
#define PCI_REG_SBUS 0x19 // Secondary Bus Number Register
#define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register
#define PCI_REG_SMLT 0x1b // Secondary Master Latnecy Timer
#define PCI_REG_IOBASE 0x1c // I/O base Register
#define PCI_REG_IOLIMIT 0x1d // I/O Limit Register
#define PCI_REG_SECSTATUS 0x1e // Secondary Status Register
#define PCI_REG_MEMBASE 0x20 // Memory Base Register
#define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register
#define PCI_REG_PRE_MEMBASE 0x24 // Prefretchable memory Base register
#define PCI_REG_PRE_MEMLIMIT 0x26 // Prefretchable memory Limit register
#define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte
#define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte
#define PCI_REG_SID0 0x2e // Subsystem ID low byte
#define PCI_REG_SID1 0x2f // Subsystem ID high byte
#define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register
#define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register
#define PCI_REG_INTLINE 0x3c // Interrupt Line Register
#define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register
//---------------------------------------------------------------------------
// QuarkSCSocId Packet Hub definitions
//---------------------------------------------------------------------------
#define PCIE_BRIDGE_VID_DID 0x88008086
//---------------------------------------------------------------------------
// Quark South Cluster definitions.
//---------------------------------------------------------------------------
#define IOH_BUS 0
#define IOH_PCI_IOSF2AHB_0_DEV_NUM 0x14
#define IOH_PCI_IOSF2AHB_0_MAX_FUNCS 7
#define IOH_PCI_IOSF2AHB_1_DEV_NUM 0x15
#define IOH_PCI_IOSF2AHB_1_MAX_FUNCS 3
//---------------------------------------------------------------------------
// Quark South Cluster USB definitions.
//---------------------------------------------------------------------------
#define IOH_USB_BUS_NUMBER IOH_BUS
#define IOH_USB_CONTROLLER_MMIO_RANGE 0x1000
#define IOH_MAX_OHCI_USB_CONTROLLERS 1
#define IOH_MAX_EHCI_USB_CONTROLLERS 1
#define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1
#define R_IOH_USB_VENDOR_ID 0x00
#define V_IOH_USB_VENDOR_ID INTEL_VENDOR_ID
#define R_IOH_USB_DEVICE_ID 0x02
#define R_IOH_USB_COMMAND 0x04
#define B_IOH_USB_COMMAND_BME BIT2
#define B_IOH_USB_COMMAND_MSE BIT1
#define B_IOH_USB_COMMAND_ISE BIT0
#define R_IOH_USB_MEMBAR 0x10
#define B_IOH_USB_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
#define R_IOH_USB_OHCI_HCCABAR 0x18
//---------------------------------------------------------------------------
// Quark South Cluster OHCI definitions
//---------------------------------------------------------------------------
#define IOH_USB_OHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
#define IOH_OHCI_FUNCTION_NUMBER 0x04
//---------------------------------------------------------------------------
// Quark South Cluster EHCI definitions
//---------------------------------------------------------------------------
#define IOH_USB_EHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
#define IOH_EHCI_FUNCTION_NUMBER 0x03
//
// EHCI memory mapped registers offset from memory BAR0.
//
#define R_IOH_EHCI_CAPLENGTH 0x00
#define R_IOH_EHCI_INSNREG01 0x94
#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16)
#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0)
#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)
//
// EHCI memory mapped registers offset from memory BAR0 + Cap length value.
//
#define R_IOH_EHCI_CONFIGFLAGS 0x40
//---------------------------------------------------------------------------
// Quark South Cluster USB Device definitions
//---------------------------------------------------------------------------
#define IOH_USBDEVICE_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
#define IOH_USBDEVICE_FUNCTION_NUMBER 0x02
//
// USB Device memory mapped registers offset from memory BAR0.
//
#define R_IOH_USBDEVICE_D_INTR_UDC_REG 0x40c
#define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG 0x410
#define B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK 0xff
#define R_IOH_USBDEVICE_EP_INTR_UDC_REG 0x414
#define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG 0x418
#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK 0x000f0000
#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK 0x0000000f
//---------------------------------------------------------------------------
// Quark South Cluster 10/100 Mbps Ethernet Device definitions.
//---------------------------------------------------------------------------
#define IOH_MAC0_BUS_NUMBER IOH_BUS
#define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
#define IOH_MAC0_FUNCTION_NUMBER 0x06
#define IOH_MAC1_BUS_NUMBER IOH_BUS
#define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
#define IOH_MAC1_FUNCTION_NUMBER 0x07
//
// MAC Device PCI config registers.
//
#define R_IOH_MAC_DEVICE_ID 0x02
#define V_IOH_MAC_VENDOR_ID INTEL_VENDOR_ID
#define R_IOH_MAC_DEVICE_ID 0x02
#define V_IOH_MAC_DEVICE_ID 0x0937
#define R_IOH_MAC_COMMAND 0x04
#define B_IOH_MAC_COMMAND_BME BIT2
#define B_IOH_MAC_COMMAND_MSE BIT1
#define B_IOH_MAC_COMMAND_ISE BIT0
#define R_IOH_MAC_MEMBAR 0x10
#define B_IOH_MAC_MEMBAR_ADDRESS_MASK 0xFFFFF000
//
// LAN Device memory mapped registers offset from memory BAR0.
//
#define R_IOH_MAC_GMAC_REG_8 0x20
#define B_IOH_MAC_USERVER_MASK 0x0000FF00
#define B_IOH_MAC_SNPSVER_MASK 0x000000FF
#define R_IOH_MAC_GMAC_REG_16 0x40
#define B_IOH_MAC_ADDRHI_MASK 0x0000FFFF
#define B_IOH_MAC_AE BIT31
#define R_IOH_MAC_GMAC_REG_17 0x44
#define B_IOH_MAC_ADDRLO_MASK 0xFFFFFFFF
//---------------------------------------------------------------------------
// Quark I2C / GPIO definitions
//---------------------------------------------------------------------------
#define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID
#define V_IOH_I2C_GPIO_DEVICE_ID 0x0934
#define R_IOH_I2C_MEMBAR 0x10
#define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].
#define GPIO_SWPORTA_DR 0x00
#define GPIO_SWPORTA_DDR 0x04
#define GPIO_INTEN 0x30
#define GPIO_INTMASK 0x34
#define GPIO_INTTYPE_LEVEL 0x38
#define GPIO_INT_POLARITY 0x3C
#define GPIO_INTSTATUS 0x40
#define GPIO_RAW_INTSTATUS 0x44
#define GPIO_DEBOUNCE 0x48
#define GPIO_PORTA_EOI 0x4C
#define GPIO_EXT_PORTA 0x50
#define GPIO_EXT_PORTB 0x54
#define GPIO_LS_SYNC 0x60
#define GPIO_CONFIG_REG2 0x70
#define GPIO_CONFIG_REG1 0x74
//---------------------------------------------------------------------------
// Quark South Cluster UART definitions.
//---------------------------------------------------------------------------
#define R_IOH_UART_MEMBAR 0x10
#define B_IOH_UART_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
#endif

24
QuarkSocPkg/QuarkSouthCluster/Include/IohAccess.h Normal file
View File

@@ -0,0 +1,24 @@
/** @file
Macros to simplify and abstract the interface to PCI configuration.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IOH_ACCESS_H_
#define _IOH_ACCESS_H_
#include "Ioh.h"
#include "IohCommonDefinitions.h"
#endif

348
QuarkSocPkg/QuarkSouthCluster/Include/IohCommonDefinitions.h Normal file
View File

@@ -0,0 +1,348 @@
/** @file
This header file provides common definitions just for MCH using to avoid including extra module's file.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IOH_COMMON_DEFINITIONS_H_
#define _IOH_COMMON_DEFINITIONS_H_
//
// PCI CONFIGURATION MAP REGISTER OFFSETS
//
#ifndef PCI_VID
#define PCI_VID 0x0000 // Vendor ID Register
#define PCI_DID 0x0002 // Device ID Register
#define PCI_CMD 0x0004 // PCI Command Register
#define PCI_STS 0x0006 // PCI Status Register
#define PCI_RID 0x0008 // Revision ID Register
#define PCI_IFT 0x0009 // Interface Type
#define PCI_SCC 0x000A // Sub Class Code Register
#define PCI_BCC 0x000B // Base Class Code Register
#define PCI_CLS 0x000C // Cache Line Size
#define PCI_PMLT 0x000D // Primary Master Latency Timer
#define PCI_HDR 0x000E // Header Type Register
#define PCI_BIST 0x000F // Built in Self Test Register
#define PCI_BAR0 0x0010 // Base Address Register 0
#define PCI_BAR1 0x0014 // Base Address Register 1
#define PCI_BAR2 0x0018 // Base Address Register 2
#define PCI_PBUS 0x0018 // Primary Bus Number Register
#define PCI_SBUS 0x0019 // Secondary Bus Number Register
#define PCI_SUBUS 0x001A // Subordinate Bus Number Register
#define PCI_SMLT 0x001B // Secondary Master Latency Timer
#define PCI_BAR3 0x001C // Base Address Register 3
#define PCI_IOBASE 0x001C // I/O base Register
#define PCI_IOLIMIT 0x001D // I/O Limit Register
#define PCI_SECSTATUS 0x001E // Secondary Status Register
#define PCI_BAR4 0x0020 // Base Address Register 4
#define PCI_MEMBASE 0x0020 // Memory Base Register
#define PCI_MEMLIMIT 0x0022 // Memory Limit Register
#define PCI_BAR5 0x0024 // Base Address Register 5
#define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register
#define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register
#define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits
#define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits
#define PCI_SVID 0x002C // Subsystem Vendor ID
#define PCI_SID 0x002E // Subsystem ID
#define PCI_IOBASE_U 0x0030 // I/O base Upper Register
#define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register
#define PCI_CAPP 0x0034 // Capabilities Pointer
#define PCI_EROM 0x0038 // Expansion ROM Base Address
#define PCI_INTLINE 0x003C // Interrupt Line Register
#define PCI_INTPIN 0x003D // Interrupt Pin Register
#define PCI_MAXGNT 0x003E // Max Grant Register
#define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register
#define PCI_MAXLAT 0x003F // Max Latency Register
#endif
//
// Bit Difinitions
//
#ifndef BIT0
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#endif
//
// Common Memory mapped Io access macros ------------------------------------------
//
#define IohMmioAddress( BaseAddr, Register ) \
( (UINTN)BaseAddr + \
(UINTN)(Register) \
)
//
// UINT64
//
#define IohMmio64Ptr( BaseAddr, Register ) \
( (volatile UINT64 *)IohMmioAddress( BaseAddr, Register ) )
#define IohMmio64( BaseAddr, Register ) \
*IohMmio64Ptr( BaseAddr, Register )
#define IohMmio64Or( BaseAddr, Register, OrData ) \
IohMmio64( BaseAddr, Register ) = \
(UINT64) ( \
IohMmio64( BaseAddr, Register ) | \
(UINT64)(OrData) \
)
#define IohMmio64And( BaseAddr, Register, AndData ) \
IohMmio64( BaseAddr, Register ) = \
(UINT64) ( \
IohMmio64( BaseAddr, Register ) & \
(UINT64)(AndData) \
)
#define IohMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \
IohMmio64( BaseAddr, Register ) = \
(UINT64) ( \
( IohMmio64( BaseAddr, Register ) & \
(UINT64)(AndData) \
) | \
(UINT64)(OrData) \
)
//
// UINT32
//
#define IohMmio32Ptr( BaseAddr, Register ) \
( (volatile UINT32 *)IohMmioAddress( BaseAddr, Register ) )
#define IohMmio32( BaseAddr, Register ) \
*IohMmio32Ptr( BaseAddr, Register )
#define IohMmio32Or( BaseAddr, Register, OrData ) \
IohMmio32( BaseAddr, Register ) = \
(UINT32) ( \
IohMmio32( BaseAddr, Register ) | \
(UINT32)(OrData) \
)
#define IohMmio32And( BaseAddr, Register, AndData ) \
IohMmio32( BaseAddr, Register ) = \
(UINT32) ( \
IohMmio32( BaseAddr, Register ) & \
(UINT32)(AndData) \
)
#define IohMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
IohMmio32( BaseAddr, Register ) = \
(UINT32) ( \
( IohMmio32( BaseAddr, Register ) & \
(UINT32)(AndData) \
) | \
(UINT32)(OrData) \
)
//
// UINT16
//
#define IohMmio16Ptr( BaseAddr, Register ) \
( (volatile UINT16 *)IohMmioAddress( BaseAddr, Register ) )
#define IohMmio16( BaseAddr, Register ) \
*IohMmio16Ptr( BaseAddr, Register )
#define IohMmio16Or( BaseAddr, Register, OrData ) \
IohMmio16( BaseAddr, Register ) = \
(UINT16) ( \
IohMmio16( BaseAddr, Register ) | \
(UINT16)(OrData) \
)
#define IohMmio16And( BaseAddr, Register, AndData ) \
IohMmio16( BaseAddr, Register ) = \
(UINT16) ( \
IohMmio16( BaseAddr, Register ) & \
(UINT16)(AndData) \
)
#define IohMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
IohMmio16( BaseAddr, Register ) = \
(UINT16) ( \
( IohMmio16( BaseAddr, Register ) & \
(UINT16)(AndData) \
) | \
(UINT16)(OrData) \
)
//
// UINT8
//
#define IohMmio8Ptr( BaseAddr, Register ) \
( (volatile UINT8 *)IohMmioAddress( BaseAddr, Register ) )
#define IohMmio8( BaseAddr, Register ) \
*IohMmio8Ptr( BaseAddr, Register )
#define IohMmio8Or( BaseAddr, Register, OrData ) \
IohMmio8( BaseAddr, Register ) = \
(UINT8) ( \
IohMmio8( BaseAddr, Register ) | \
(UINT8)(OrData) \
)
#define IohMmio8And( BaseAddr, Register, AndData ) \
IohMmio8( BaseAddr, Register ) = \
(UINT8) ( \
IohMmio8( BaseAddr, Register ) & \
(UINT8)(AndData) \
)
#define IohMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
IohMmio8( BaseAddr, Register ) = \
(UINT8) ( \
( IohMmio8( BaseAddr, Register ) & \
(UINT8)(AndData) \
) | \
(UINT8)(OrData) \
)
//
// Common Memory mapped Pci access macros ------------------------------------------
//
#define Ioh_PCI_EXPRESS_BASE_ADDRESS 0xE0000000
#define IohMmPciAddress( Segment, Bus, Device, Function, Register ) \
( (UINTN)Ioh_PCI_EXPRESS_BASE_ADDRESS + \
(UINTN)(Bus << 20) + \
(UINTN)(Device << 15) + \
(UINTN)(Function << 12) + \
(UINTN)(Register) \
)
//
// UINT32
//
#define IohMmPci32Ptr( Segment, Bus, Device, Function, Register ) \
( (volatile UINT32 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )
#define IohMmPci32( Segment, Bus, Device, Function, Register ) \
*IohMmPci32Ptr( Segment, Bus, Device, Function, Register )
#define IohMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
IohMmPci32( Segment, Bus, Device, Function, Register ) = \
(UINT32) ( \
IohMmPci32( Segment, Bus, Device, Function, Register ) | \
(UINT32)(OrData) \
)
#define IohMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
IohMmPci32( Segment, Bus, Device, Function, Register ) = \
(UINT32) ( \
IohMmPci32( Segment, Bus, Device, Function, Register ) & \
(UINT32)(AndData) \
)
#define IohMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
IohMmPci32( Segment, Bus, Device, Function, Register ) = \
(UINT32) ( \
( IohMmPci32( Segment, Bus, Device, Function, Register ) & \
(UINT32)(AndData) \
) | \
(UINT32)(OrData) \
)
//
// UINT16
//
#define IohMmPci16Ptr( Segment, Bus, Device, Function, Register ) \
( (volatile UINT16 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )
#define IohMmPci16( Segment, Bus, Device, Function, Register ) \
*IohMmPci16Ptr( Segment, Bus, Device, Function, Register )
#define IohMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
IohMmPci16( Segment, Bus, Device, Function, Register ) = \
(UINT16) ( \
IohMmPci16( Segment, Bus, Device, Function, Register ) | \
(UINT16)(OrData) \
)
#define IohMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
IohMmPci16( Segment, Bus, Device, Function, Register ) = \
(UINT16) ( \
IohMmPci16( Segment, Bus, Device, Function, Register ) & \
(UINT16)(AndData) \
)
#define IohMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
IohMmPci16( Segment, Bus, Device, Function, Register ) = \
(UINT16) ( \
( IohMmPci16( Segment, Bus, Device, Function, Register ) & \
(UINT16)(AndData) \
) | \
(UINT16)(OrData) \
)
//
// UINT8
//
#define IohMmPci8Ptr( Segment, Bus, Device, Function, Register ) \
( (volatile UINT8 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )
#define IohMmPci8( Segment, Bus, Device, Function, Register ) \
*IohMmPci8Ptr( Segment, Bus, Device, Function, Register )
#define IohMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
IohMmPci8( Segment, Bus, Device, Function, Register ) = \
(UINT8) ( \
IohMmPci8( Segment, Bus, Device, Function, Register ) | \
(UINT8)(OrData) \
)
#define IohMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
IohMmPci8( Segment, Bus, Device, Function, Register ) = \
(UINT8) ( \
IohMmPci8( Segment, Bus, Device, Function, Register ) & \
(UINT8)(AndData) \
)
#define IohMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
IohMmPci8( Segment, Bus, Device, Function, Register ) = \
(UINT8) ( \
( IohMmPci8( Segment, Bus, Device, Function, Register ) & \
(UINT8)(AndData) \
) | \
(UINT8)(OrData) \
)
#endif

158
QuarkSocPkg/QuarkSouthCluster/Include/Library/I2cLib.h Normal file
View File

@@ -0,0 +1,158 @@
/** @file
Intel I2C library implementation built upon I/O library
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _I2C_LIB_H_
#define _I2C_LIB_H_
#include "I2cRegs.h"
/**
The I2cWriteByte() function is a wrapper function for the WriteByte() function.
Provides a standard way to execute a standard single byte write to an IC2 device
(without accessing sub-addresses), as defined in the I2C Specification.
@param SlaveAddress The I2C slave address of the device
with which to communicate.
@param AddrMode I2C Addressing Mode: 7-bit or 10-bit address.
@param Buffer Contains the value of byte data to execute to the
I2C slave device.
@retval EFI_SUCCESS Transfer success.
@retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
@retval EFI_TIMEOUT Timeout while waiting xfer.
@retval EFI_ABORTED Controller aborted xfer.
@retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
EFIAPI
I2cWriteByte (
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
IN OUT VOID *Buffer
);
/**
The I2cReadByte() function is a wrapper function for the ReadByte() function.
Provides a standard way to execute a standard single byte read to an I2C device
(without accessing sub-addresses), as defined in the I2C Specification.
@param SlaveAddress The I2C slave address of the device
with which to communicate.
@param AddrMode I2C Addressing Mode: 7-bit or 10-bit address.
@param Buffer Contains the value of byte data read from the
I2C slave device.
@retval EFI_SUCCESS Transfer success.
@retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
@retval EFI_TIMEOUT Timeout while waiting xfer.
@retval EFI_ABORTED Controller aborted xfer.
@retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
EFIAPI
I2cReadByte (
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
IN OUT VOID *Buffer
);
/**
The I2cWriteMultipleByte() function is a wrapper function for the WriteMultipleByte()
function. Provides a standard way to execute multiple byte writes to an I2C device (e.g. when
accessing sub-addresses or writing block of data), as defined in the I2C Specification.
@param SlaveAddress The I2C slave address of the device
with which to communicate.
@param AddrMode I2C Addressing Mode: 7-bit or 10-bit address.
@param Length No. of bytes to be written.
@param Buffer Contains the value of byte to be written to the
I2C slave device.
@retval EFI_SUCCESS Transfer success.
@retval EFI_INVALID_PARAMETER This, Length or Buffer pointers are invalid.
@retval EFI_UNSUPPORTED Unsupported input param.
@retval EFI_TIMEOUT Timeout while waiting xfer.
@retval EFI_ABORTED Controller aborted xfer.
@retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
EFIAPI
I2cWriteMultipleByte (
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
IN UINTN *Length,
IN OUT VOID *Buffer
);
/**
The I2cReadMultipleByte() function is a wrapper function for the ReadMultipleByte
function. Provides a standard way to execute multiple byte writes to an IC2 device
(e.g. when accessing sub-addresses or when reading block of data), as defined
in the I2C Specification (I2C combined write/read protocol).
@param SlaveAddress The I2C slave address of the device
with which to communicate.
@param AddrMode I2C Addressing Mode: 7-bit or 10-bit address.
@param WriteLength No. of bytes to be written. In this case data
written typically contains sub-address or sub-addresses
in Hi-Lo format, that need to be read (I2C combined
write/read protocol).
@param ReadLength No. of bytes to be read from I2C slave device.
need to be read.
@param Buffer Contains the value of byte data read from the
I2C slave device.
@retval EFI_SUCCESS Transfer success.
@retval EFI_INVALID_PARAMETER This, WriteLength, ReadLength or Buffer
pointers are invalid.
@retval EFI_UNSUPPORTED Unsupported input param.
@retval EFI_TIMEOUT Timeout while waiting xfer.
@retval EFI_ABORTED Controller aborted xfer.
@retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
EFIAPI
I2cReadMultipleByte (
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
IN UINTN *WriteLength,
IN UINTN *ReadLength,
IN OUT VOID *Buffer
);
#endif

42
QuarkSocPkg/QuarkSouthCluster/Include/Library/IohLib.h Normal file
View File

@@ -0,0 +1,42 @@
/** @file
Library that provides Soc specific library services for SouthCluster devices.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __IOH_LIB_H__
#define __IOH_LIB_H__
#include "Ioh.h"
EFI_STATUS
EFIAPI
InitializeIohSsvidSsid (
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
VOID
EFIAPI
EnableUsbMemIoBusMaster (
IN UINT8 UsbBusNumber
);
UINT32
EFIAPI
ReadIohGpioValues (
VOID
);
#endif

280
QuarkSocPkg/QuarkSouthCluster/Include/MMC.h Normal file
View File

@@ -0,0 +1,280 @@
/** @file
Header file for Industry MMC 4.2 spec.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MMC_H
#define _MMC_H
#pragma pack(1)
//
//Command definition
//
#define CMD0 0
#define CMD1 1
#define CMD2 2
#define CMD3 3
#define CMD4 4
#define CMD6 6
#define CMD7 7
#define CMD8 8
#define CMD9 9
#define CMD10 10
#define CMD11 11
#define CMD12 12
#define CMD13 13
#define CMD14 14
#define CMD15 15
#define CMD16 16
#define CMD17 17
#define CMD18 18
#define CMD19 19
#define CMD20 20
#define CMD23 23
#define CMD24 24
#define CMD25 25
#define CMD26 26
#define CMD27 27
#define CMD28 28
#define CMD29 29
#define CMD30 30
#define CMD35 35
#define CMD36 36
#define CMD38 38
#define CMD39 39
#define CMD40 40
#define CMD42 42
#define CMD55 55
#define CMD56 56
#define GO_IDLE_STATE CMD0
#define SEND_OP_COND CMD1
#define ALL_SEND_CID CMD2
#define SET_RELATIVE_ADDR CMD3
#define SET_DSR CMD4
#define SWITCH CMD6
#define SELECT_DESELECT_CARD CMD7
#define SEND_EXT_CSD CMD8
#define SEND_CSD CMD9
#define SEND_CID CMD10
#define READ_DAT_UNTIL_STOP CMD11
#define STOP_TRANSMISSION CMD12
#define SEND_STATUS CMD13
#define BUSTEST_R CMD14
#define GO_INACTIVE_STATE CMD15
#define SET_BLOCKLEN CMD16
#define READ_SINGLE_BLOCK CMD17
#define READ_MULTIPLE_BLOCK CMD18
#define BUSTEST_W CMD19
#define WRITE_DAT_UNTIL_STOP CMD20
#define SET_BLOCK_COUNT CMD23
#define WRITE_BLOCK CMD24
#define WRITE_MULTIPLE_BLOCK CMD25
#define PROGRAM_CID CMD26
#define PROGRAM_CSD CMD27
#define SET_WRITE_PROT CMD28
#define CLR_WRITE_PROT CMD29
#define SEND_WRITE_PROT CMD30
#define ERASE_GROUP_START CMD35
#define ERASE_GROUP_END CMD36
#define ERASE CMD38
#define FAST_IO CMD39
#define GO_IRQ_STATE CMD40
#define LOCK_UNLOCK CMD42
#define APP_CMD CMD55
#define GEN_CMD CMD56
#define CMD_INDEX_MASK 0x3F
#define AUTO_CMD12_ENABLE BIT6
#define AUTO_CMD23_ENABLE BIT7
#define FREQUENCY_OD (400 * 1000)
#define FREQUENCY_MMC_PP (26 * 1000 * 1000)
#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)
#define DEFAULT_DSR_VALUE 0x404
//
//Registers definition
//
typedef struct {
UINT32 Reserved0: 7; // 0
UINT32 V170_V195: 1; // 1.70V - 1.95V
UINT32 V200_V260: 7; // 2.00V - 2.60V
UINT32 V270_V360: 9; // 2.70V - 3.60V
UINT32 Reserved1: 5; // 0
UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
}OCR;
typedef struct {
UINT8 NotUsed: 1; // 1
UINT8 CRC: 7; // CRC7 checksum
UINT8 MDT; // Manufacturing date
UINT32 PSN; // Product serial number
UINT8 PRV; // Product revision
UINT8 PNM[6]; // Product name
UINT16 OID; // OEM/Application ID
UINT8 MID; // Manufacturer ID
}CID;
typedef struct {
UINT8 NotUsed: 1; // 1 [0:0]
UINT8 CRC: 7; // CRC [7:1]
UINT8 ECC: 2; // ECC code [9:8]
UINT8 FILE_FORMAT: 2; // File format [11:10]
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]
UINT16 Reserved0: 4; // 0 [20:17]
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]
UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]
UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]
UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
UINT32 C_SIZELow2: 2;// Device size [73:62]
UINT32 C_SIZEHigh10: 10;// Device size [73:62]
UINT32 Reserved1: 2; // 0 [75:74]
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
UINT32 CCC: 12;// Card command classes [95:84]
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT8 TAAC ; // Data read access-time 1 [119:112]
UINT8 Reserved2: 2; // 0 [121:120]
UINT8 SPEC_VERS: 4; // System specification version [125:122]
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
}CSD;
typedef struct {
UINT8 Reserved0[181]; // 0 [0:180]
UINT8 ERASED_MEM_CONT; // Erased Memory Content [181]
UINT8 Reserved2; // Erased Memory Content [182]
UINT8 BUS_WIDTH; // Bus Width Mode [183]
UINT8 Reserved3; // 0 [184]
UINT8 HS_TIMING; // High Speed Interface Timing [185]
UINT8 Reserved4; // 0 [186]
UINT8 POWER_CLASS; // Power Class [187]
UINT8 Reserved5; // 0 [188]
UINT8 CMD_SET_REV; // Command Set Revision [189]
UINT8 Reserved6; // 0 [190]
UINT8 CMD_SET; // Command Set [191]
UINT8 EXT_CSD_REV; // Extended CSD Revision [192]
UINT8 Reserved7; // 0 [193]
UINT8 CSD_STRUCTURE; // CSD Structure Version [194]
UINT8 Reserved8; // 0 [195]
UINT8 CARD_TYPE; // Card Type [196]
UINT8 Reserved9[3]; // 0 [199:197]
UINT8 PWR_CL_52_195; // Power Class for 52MHz @ 1.95V [200]
UINT8 PWR_CL_26_195; // Power Class for 26MHz @ 1.95V [201]
UINT8 PWR_CL_52_360; // Power Class for 52MHz @ 3.6V [202]
UINT8 PWR_CL_26_360; // Power Class for 26MHz @ 3.6V [203]
UINT8 Reserved10; // 0 [204]
UINT8 MIN_PERF_R_4_26; // Minimum Read Performance for 4bit @26MHz [205]
UINT8 MIN_PERF_W_4_26; // Minimum Write Performance for 4bit @26MHz [206]
UINT8 MIN_PERF_R_8_26_4_52; // Minimum Read Performance for 8bit @26MHz/4bit @52MHz [207]
UINT8 MIN_PERF_W_8_26_4_52; // Minimum Write Performance for 8bit @26MHz/4bit @52MHz [208]
UINT8 MIN_PERF_R_8_52; // Minimum Read Performance for 8bit @52MHz [209]
UINT8 MIN_PERF_W_8_52; // Minimum Write Performance for 8bit @52MHz [210]
UINT8 Reserved11; // 0 [211]
UINT8 SEC_COUNT[4]; // Sector Count [215:212]
UINT8 Reserved12[288]; // 0 [503:216]
UINT8 S_CMD_SET; // Sector Count [504]
UINT8 Reserved13[7]; // Sector Count [511:505]
}EXT_CSD;
//
//Card Status definition
//
typedef struct {
UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode
UINT32 Reserved1: 2; //Reserved for Application Specific commands
UINT32 Reserved2: 1; //
UINT32 SAPP_CMD: 1; //
UINT32 Reserved3: 1; //Reserved
UINT32 SWITCH_ERROR: 1; //
UINT32 READY_FOR_DATA: 1; //
UINT32 CURRENT_STATE: 4; //
UINT32 ERASE_RESET: 1; //
UINT32 Reserved4: 1; //Reserved
UINT32 WP_ERASE_SKIP: 1; //
UINT32 CID_CSD_OVERWRITE: 1; //
UINT32 OVERRUN: 1; //
UINT32 UNDERRUN: 1; //
UINT32 ERROR: 1; //
UINT32 CC_ERROR: 1; //
UINT32 CARD_ECC_FAILED: 1; //
UINT32 ILLEGAL_COMMAND: 1; //
UINT32 COM_CRC_ERROR: 1; //
UINT32 LOCK_UNLOCK_FAILED: 1; //
UINT32 CARD_IS_LOCKED: 1; //
UINT32 WP_VIOLATION: 1; //
UINT32 ERASE_PARAM: 1; //
UINT32 ERASE_SEQ_ERROR: 1; //
UINT32 BLOCK_LEN_ERROR: 1; //
UINT32 ADDRESS_MISALIGN: 1; //
UINT32 ADDRESS_OUT_OF_RANGE:1; //
}CARD_STATUS;
typedef struct {
UINT32 CmdSet: 3;
UINT32 Reserved0: 5;
UINT32 Value: 8;
UINT32 Index: 8;
UINT32 Access: 2;
UINT32 Reserved1: 6;
}SWITCH_ARGUMENT;
#define CommandSet_Mode 0
#define SetBits_Mode 1
#define ClearBits_Mode 2
#define WriteByte_Mode 3
#define Idle_STATE 0
#define Ready_STATE 1
#define Ident_STATE 2
#define Stby_STATE 3
#define Tran_STATE 4
#define Data_STATE 5
#define Rcv_STATE 6
#define Prg_STATE 7
#define Dis_STATE 8
#define Btst_STATE 9
#pragma pack()
#endif

152
QuarkSocPkg/QuarkSouthCluster/Include/SDCard.h Normal file
View File

@@ -0,0 +1,152 @@
/** @file
Header file for Industry SD Card 2.0 spec.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SD_CARD_H
#define _SD_CARD_H
#include "MMC.h"
#pragma pack(1)
#define CHECK_PATTERN 0xAA ///< Physical Layer Simplified Specification Version 3.01 recommended 0xAA
#define ACMD6 6
#define ACMD13 13
#define ACMD23 23
#define ACMD41 41
#define ACMD42 42
#define ACMD51 51
#define SWITCH_FUNC CMD6
#define SEND_IF_COND CMD8
#define SET_BUS_WIDTH ACMD6
#define SD_STATUS ACMD13
#define SET_WR_BLK_ERASE_COUNT ACMD23
#define SD_SEND_OP_COND ACMD41
#define SET_CLR_CARD_DETECT ACMD42
#define SEND_SCR ACMD51
#define SD_BUS_WIDTH_1 0
#define SD_BUS_WIDTH_4 2
#define FREQUENCY_SD_PP (25 * 1000 * 1000)
#define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000)
#define SD_SPEC_10 0
#define SD_SPEC_11 1
#define SD_SPEC_20 2
#define VOLTAGE_27_36 0x1
typedef struct {
UINT8 NotUsed: 1; // 1 [0:0]
UINT8 CRC: 7; // CRC [7:1]
UINT8 ECC: 2; // ECC code [9:8]
UINT8 FILE_FORMAT: 2; // File format [11:10]
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
UINT16 Reserved0: 5; // 0 [20:16]
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
UINT16 Reserved1: 1; // 0 [47:47]
UINT32 C_SIZE: 22; // Device size [69:48]
UINT32 Reserved2: 6; // 0 [75:70]
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
UINT16 CCC: 12; // Card command classes [95:84]
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT8 TAAC ; // Data read access-time 1 [119:112]
UINT8 Reserved3: 6; // 0 [125:120]
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
}CSD_SDV2;
typedef struct {
UINT32 Reserved0;
UINT32 Reserved1: 16;
UINT32 SD_BUS_WIDTH: 4;
UINT32 SD_SECURITY: 3;
UINT32 DATA_STAT_AFTER_ERASE: 1;
UINT32 SD_SPEC: 4;
UINT32 SCR_STRUCT: 4;
}SCR;
typedef struct {
UINT8 Reserved0[50];
UINT8 ERASE_OFFSET: 2;
UINT8 ERASE_TIMEOUT: 6;
UINT16 ERASE_SIZE;
UINT8 Reserved1: 4;
UINT8 AU_SIZE: 4;
UINT8 PERFORMANCE_MOVE;
UINT8 SPEED_CLASS;
UINT32 SIZE_OF_PROTECTED_AREA;
UINT32 SD_CARD_TYPE: 16;
UINT32 Reserved2: 13;
UINT32 SECURED_MODE: 1;
UINT32 DAT_BUS_WIDTH: 2;
}SD_STATUS_REG;
typedef struct {
UINT8 Reserved0[34];
UINT16 Group1BusyStatus;
UINT16 Group2BusyStatus;
UINT16 Group3BusyStatus;
UINT16 Group4BusyStatus;
UINT16 Group5BusyStatus;
UINT16 Group6BusyStatus;
UINT8 DataStructureVersion;
UINT8 Group21Status;
UINT8 Group43Status;
UINT8 Group65Status;
UINT16 Group1Function;
UINT16 Group2Function;
UINT16 Group3Function;
UINT16 Group4Function;
UINT16 Group5Function;
UINT16 Group6Function;
UINT16 MaxCurrent;
}SWITCH_STATUS;
#pragma pack()
#endif

339
QuarkSocPkg/QuarkSouthCluster/Include/SDHostIo.h Normal file
View File

@@ -0,0 +1,339 @@
/** @file
Interface definition for EFI_SD_HOST_IO_PROTOCOL.
Copyright (c) 2013-2015 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SD_HOST_IO_H
#define _SD_HOST_IO_H
#include "SDCard.h"
#include "CEATA.h"
#define EFI_SD_HOST_IO_PROTOCOL_GUID \
{ \
0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51} \
}
///
/// Forward reference for pure ANSI compatability
///
typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL;
typedef enum {
ResponseNo = 0,
ResponseR1,
ResponseR1b,
ResponseR2,
ResponseR3,
ResponseR4,
ResponseR5,
ResponseR5b,
ResponseR6,
ResponseR7
}RESPONSE_TYPE;
typedef enum {
NoData = 0,
InData,
OutData
}TRANSFER_TYPE;
typedef enum {
Reset_Auto = 0,
Reset_DAT,
Reset_CMD,
Reset_DAT_CMD,
Reset_All
}RESET_TYPE;
#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
#define PCI_IF_STANDARD_HOST_NO_DMA 0x00
#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
#define SDHCI_SPEC_100 0
#define SDHCI_SPEC_200 1
#define SDHCI_SPEC_300 2
//
//MMIO Registers definition for MMC/SDIO controller
//
#define MMIO_DMAADR 0x00
#define MMIO_BLKSZ 0x04
#define MMIO_BLKCNT 0x06
#define MMIO_CMDARG 0x08
#define MMIO_XFRMODE 0x0C
#define MMIO_SDCMD 0x0E
#define MMIO_RESP 0x10
#define MMIO_BUFDATA 0x20
#define MMIO_PSTATE 0x24
#define MMIO_HOSTCTL 0x28
#define MMIO_PWRCTL 0x29
#define MMIO_BLKGAPCTL 0x2A
#define MMIO_WAKECTL 0x2B
#define MMIO_CLKCTL 0x2C
#define V_MMIO_CLKCTL_MAX_8BIT_FREQ_SEL 0x80
#define V_MMIO_CLKCTL_MAX_10BIT_FREQ_SEL 0x3FF
#define B_MMIO_CLKCTL_UPR_SDCLK_FREQ_SEL_MASK 0xC0
#define MMIO_TOCTL 0x2E
#define MMIO_SWRST 0x2F
#define MMIO_NINTSTS 0x30
#define MMIO_ERINTSTS 0x32
#define MMIO_NINTEN 0x34
#define MMIO_ERINTEN 0x36
#define MMIO_NINTSIGEN 0x38
#define MMIO_ERINTSIGEN 0x3A
#define MMIO_AC12ERRSTS 0x3C
#define MMIO_HOSTCTL2 0x3E
#define MMIO_CAP 0x40
#define MMIO_MCCAP 0x48
#define MMIO_SLTINTSTS 0xFC
#define MMIO_CTRLRVER 0xFE
#define MMIO_SRST 0x1FC
//
// Protocol definitions
//
/**
The main function used to send the command to the card inserted into the SD host slot.
It will assemble the arguments to set the command register and wait for the command
and transfer completed until timeout. Then it will read the response register to fill
the ResponseData.
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param CommandIndex The command index to set the command index field of command register.
@param Argument Command argument to set the argument field of command register.
@param DataType TRANSFER_TYPE, indicates no data, data in or data out.
@param Buffer Contains the data read from / write to the device.
@param BufferSize The size of the buffer.
@param ResponseType RESPONSE_TYPE.
@param TimeOut Time out value in 1 ms unit.
@param ResponseData Depending on the ResponseType, such as CSD or card status.
@retval EFI_SUCCESS
@retval EFI_INVALID_PARAMETER
@retval EFI_OUT_OF_RESOURCES
@retval EFI_TIMEOUT
@retval EFI_DEVICE_ERROR
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN UINT16 CommandIndex,
IN UINT32 Argument,
IN TRANSFER_TYPE DataType,
IN UINT8 *Buffer, OPTIONAL
IN UINT32 BufferSize,
IN RESPONSE_TYPE ResponseType,
IN UINT32 TimeOut,
OUT UINT32 *ResponseData OPTIONAL
);
/**
Set max clock frequency of the host, the actual frequency may not be the same as MaxFrequency.
It depends on the max frequency the host can support, divider, and host speed mode.
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param MaxFrequency Max frequency in HZ.
@retval EFI_SUCCESS
@retval EFI_TIMEOUT
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN UINT32 MaxFrequency
);
/**
Set bus width of the host controller
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param BusWidth Bus width in 1, 4, 8 bits.
@retval EFI_SUCCESS
@retval EFI_INVALID_PARAMETER
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN UINT32 BusWidth
);
/**
Set voltage which could supported by the host controller.
Support 0(Power off the host), 1.8V, 3.0V, 3.3V
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param Voltage Units in 0.1 V.
@retval EFI_SUCCESS
@retval EFI_INVALID_PARAMETER
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN UINT32 Voltage
);
/**
Reset the host controller.
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param ResetAll TRUE to reset all.
@retval EFI_SUCCESS
@retval EFI_TIMEOUT
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN RESET_TYPE ResetType
);
/**
Enable auto stop on the host controller.
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param Enable TRUE to enable, FALSE to disable.
@retval EFI_SUCCESS
@retval EFI_TIMEOUT
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN BOOLEAN Enable
);
/**
Find whether these is a card inserted into the slot. If so init the host.
If not, return EFI_NOT_FOUND.
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@retval EFI_SUCCESS
@retval EFI_NOT_FOUND
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) (
IN EFI_SD_HOST_IO_PROTOCOL *This
);
/**
Set the Block length on the host controller.
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param BlockLength card supportes block length.
@retval EFI_SUCCESS
@retval EFI_TIMEOUT
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN UINT32 BlockLength
);
/**
Enable/Disable High Speed transfer mode
@param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance.
@param Enable TRUE to Enable, FALSE to Disable
@return EFI_SUCCESS
**/
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_HIGH_SPEED_MODE) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN BOOLEAN Enable
);
typedef
EFI_STATUS
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DUAL_DATARATE_MODE) (
IN EFI_SD_HOST_IO_PROTOCOL *This,
IN BOOLEAN Enable
);
#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x02
typedef struct {
UINT32 HighSpeedSupport: 1; //High speed supported
UINT32 V18Support: 1; //1.8V supported
UINT32 V30Support: 1; //3.0V supported
UINT32 V33Support: 1; //3.3V supported
UINT32 Reserved0: 4;
UINT32 HostVersion: 8;
UINT32 BusWidth4: 1; // 4 bit width
UINT32 BusWidth8: 1; // 8 bit width
UINT32 Reserved1: 14;
UINT32 BoundarySize;
}HOST_CAPABILITY;
//
// Interface structure for the SD HOST I/O Protocol
//
struct _EFI_SD_HOST_IO_PROTOCOL {
UINT32 Revision;
HOST_CAPABILITY HostCapability;
EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand;
EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency;
EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth;
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage;
EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST ResetSDHost;
EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;
EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;
EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength;
EFI_SD_HOST_IO_PROTOCOL_HIGH_SPEED_MODE SetHighSpeedMode;
EFI_SD_HOST_IO_PROTOCOL_DUAL_DATARATE_MODE SetDDRMode;
};
extern EFI_GUID gEfiSDHostIoProtocolGuid;
#endif