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1. Save/restore ICR high 32bit value and check Delivery Status before sending IPI. It could be fix the interrupted issue between ICR high/low writes by SMI handler.

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2. Save/restore CPU Interrupt state around sending IPI. It could avoid sending IPI be interrupted by CPU interrupt handler.
3. Add note for SetApicMode() API that must not be called from an interrupt handler or SMI handler.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com>
Reviewed-by: Mudusuru, Giri <giri.p.mudusuru@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15652 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeff Fan
2014-07-11 02:36:56 +00:00
committed by vanjeff
parent d2ea3b8399
commit 9c71e1e056
3 changed files with 76 additions and 2 deletions
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5
UefiCpuPkg/Include/Library/LocalApicLib.h
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@@ -4,7 +4,7 @@
Local APIC library assumes local APIC is enabled. It does not
handles cases where local APIC is disabled.
Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -68,6 +68,9 @@ GetApicMode (
If the specified local APIC mode can't be set as current, then ASSERT.
@param ApicMode APIC mode to be set.
@note This API must not be called from an interrupt handler or SMI handler.
It may result in unpredictable behavior.
**/
VOID
EFIAPI