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UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Below code is current implementation:
  if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
    CPU_REGISTER_TABLE_WRITE_FIELD (
      ProcessorNumber,
      Msr,
      MSR_IA32_FEATURE_CONTROL,
      MSR_IA32_FEATURE_CONTROL_REGISTER,
      Bits.Lock,
      1
    );
  }

1. In first normal boot, the Bits.Lock is 0, 1 will be added
   into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
   the Bits.Lock is 1, so it will not be added into the register
   table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
   not added in register table, so it's still 0 after resume. This
   is not an expect behavior. The expect value is the value should
   always 1 after booting or resuming from S3.

The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
   the register table.
2. Some MSRs may reserve their value during warm reboot.

The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Dong, Eric
2019-08-16 11:57:30 +08:00
committed by Ray Ni
parent 95cfe6c247
commit 9c90d39b60
4 changed files with 59 additions and 130 deletions
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25
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
View File

@ -1,7 +1,7 @@
/** @file
Machine Check features.
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -319,8 +319,6 @@ LmceInitialize (
IN BOOLEAN State
)
{
MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
//
// The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program
// MSR_IA32_MISC_ENABLE for thread 0 in each core.
@ -333,17 +331,14 @@ LmceInitialize (
}
}
ASSERT (ConfigData != NULL);
MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.LmceOn,
(State) ? 1 : 0
);
}
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.LmceOn,
(State) ? 1 : 0
);
return RETURN_SUCCESS;
}