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ArmPlatformPkg/PL011Uart: Create PL011 UART driver

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This library makes the interface with the PL011 UART controller.
This library can be linked to different types of driver (Serial Console,
debugger, etc) using PL011 UART controller.


ArmPlatformPkg/PL011SerialPortLib: Use Drivers/PL011Uart

Remove the direct accesses to the PL011 UART controller to use the PL011Uart
library.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11743 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-06-03 09:31:02 +00:00
parent f0a7a8ce23
commit 9dcfb8e5c8
8 changed files with 295 additions and 56 deletions
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98
ArmPlatformPkg/Include/Drivers/PL011Uart.h
View File

@@ -15,8 +15,6 @@
#ifndef __PL011_UART_H__
#define __PL011_UART_H__
#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
// PL011 Registers
#define UARTDR 0x000
#define UARTRSR 0x004
@@ -41,23 +39,103 @@
#define UART_19200_IDIV 12
#define UART_19200_FDIV 37
// data status bits
// Data status bits
#define UART_DATA_ERROR_MASK 0x0F00
// status reg bits
// Status reg bits
#define UART_STATUS_ERROR_MASK 0x0F
// flag reg bits
// Flag reg bits
#define UART_TX_EMPTY_FLAG_MASK 0x80
#define UART_RX_FULL_FLAG_MASK 0x40
#define UART_TX_FULL_FLAG_MASK 0x20
#define UART_RX_EMPTY_FLAG_MASK 0x10
#define UART_BUSY_FLAG_MASK 0x08
// control reg bits
#define UART_CTSEN_CONTROL_MASK 0x8000
#define UART_RTSEN_CONTROL_MASK 0x4000
#define UART_RTS_CONTROL_MASK 0x0800
#define UART_DTR_CONTROL_MASK 0x0400
// Control reg bits
#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
#define PL011_UARTCR_RTS (1 << 11) // Request to send
#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
#define PL011_UARTCR_RXE (1 << 9) // Receive enable
#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
// Line Control Register Bits
#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
/*
Programmed hardware of Serial port.
@return Always return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PL011UartInitialize (
IN UINTN UartBase,
IN UINTN BaudRate,
IN UINTN LineControl
);
/**
Write data to serial device.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device.
**/
UINTN
EFIAPI
PL011UartWrite (
IN UINTN UartBase,
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
);
/**
Read data from serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.
@retval !0 Aactual number of bytes read from serial device.
**/
UINTN
EFIAPI
PL011UartRead (
IN UINTN UartBase,
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
);
/**
Check to see if any data is avaiable to be read from the debug device.
@retval EFI_SUCCESS At least one byte of data is avaiable to be read
@retval EFI_NOT_READY No data is avaiable to be read
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
**/
BOOLEAN
EFIAPI
PL011UartPoll (
IN UINTN UartBase
);
#endif