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ArmPkg: Fix coding style to follow EDK2 coding convention

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11789 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-06-11 11:15:55 +00:00
parent 838725abd7
commit 9e2b420ee9
4 changed files with 327 additions and 289 deletions
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22
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
View File

@@ -126,7 +126,7 @@ EnableInterruptSource (
RegShift = Source % 32;
// write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset), 1 << RegShift);
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
@@ -156,12 +156,12 @@ DisableInterruptSource (
return EFI_UNSUPPORTED;
}
// calculate enable register offset and bit position
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
// write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER+(4*RegOffset), 1 << RegShift);
// Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
@@ -197,7 +197,7 @@ GetInterruptSourceState (
RegOffset = Source / 32;
RegShift = Source % 32;
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset)) & (1<<RegShift)) == 0) {
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE;
} else {
*InterruptState = TRUE;
@@ -389,27 +389,27 @@ InterruptDxeInitialize (
RegOffset = i / 4;
RegShift = (i % 4) * 8;
MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR+(4*RegOffset),
PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift),
GIC_DEFAULT_PRIORITY << RegShift
);
}
// configure interrupts for cpu 0
// Configure interrupts for cpu 0
for (i = 0; i < GIC_NUM_REG_PER_INT_BYTES; i++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (i*4), 0x01010101);
}
// set binary point reg to 0x7 (no preemption)
// Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7);
// set priority mask reg to 0xff to allow all priorities through
// Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff);
// enable gic cpu interface
// Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1);
// enable gic distributor
// Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1);
ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));

76
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@@ -12,6 +12,7 @@
*
**/
#include <Uefi.h>
#include <Library/IoLib.h>
#include <Drivers/PL390Gic.h>
@@ -26,28 +27,27 @@ PL390GicSetupNonSecure (
IN INTN GicInterruptInterfaceBase
)
{
UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
//Set priority Mask so that no interrupts get through to CPU
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
// Set priority Mask so that no interrupts get through to CPU
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
//Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))
{
//Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
// Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Write to End of interrupt signal
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
}
// Write to End of interrupt signal
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
}
// Ensure all GIC interrupts are Non-Secure
MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
// Ensure all interrupts can get through the priority mask
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
}
VOID
@@ -63,12 +63,12 @@ PL390GicEnableInterruptInterface (
* Enable CPU inteface in Non-secure World
* Signal Secure Interrupts to CPU using FIQ line *
*/
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
GIC_ICCICR_ENABLE_SECURE(1) |
GIC_ICCICR_ENABLE_NS(1) |
GIC_ICCICR_ACK_CTL(0) |
GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
GIC_ICCICR_USE_SBPR(0));
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
GIC_ICCICR_ENABLE_SECURE(1) |
GIC_ICCICR_ENABLE_NS(1) |
GIC_ICCICR_ACK_CTL(0) |
GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
GIC_ICCICR_USE_SBPR(0));
}
VOID
@@ -77,7 +77,7 @@ PL390GicEnableDistributor (
IN INTN GicDistributorBase
)
{
MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
}
VOID
@@ -98,18 +98,18 @@ PL390GicAcknowledgeSgiFrom (
IN INTN CoreId
)
{
INTN InterruptId;
INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
return 1;
} else {
return 0;
}
}
UINT32
@@ -120,16 +120,16 @@ PL390GicAcknowledgeSgi2From (
IN INTN SgiId
)
{
INTN InterruptId;
INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
return 1;
} else {
return 0;
}
}