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Retired PciIncompatibleDeviceSupportLib from IntelFrameworkModulePkg.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8773 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
2009-07-07 04:00:44 +00:00
parent 7bfed576b0
commit 9eb130ff8c
21 changed files with 456 additions and 2289 deletions
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1
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h
View File

@ -41,7 +41,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DevicePathLib.h>
#include <Library/PcdLib.h>
#include <Library/PciIncompatibleDeviceSupportLib.h>
#include <Library/PeCoffLib.h>
#include <IndustryStandard/Pci.h>

4
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
View File

@ -73,7 +73,6 @@
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
[LibraryClasses]
PciIncompatibleDeviceSupportLib
PcdLib
DevicePathLib
UefiBootServicesTableLib
@ -103,9 +102,6 @@
[FeaturePcd.common]
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport
[Pcd.common]
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask
# [Event]
# ##
# # Notify event set by CreateEventForHpc () for PCI Hot Plug controller.

70
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
View File

@ -43,13 +43,13 @@ PciOperateRegister (
PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) {
Status = PciIoRead (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
if (Operation == EFI_GET_REGISTER) {
*PtrCommand = OldCommand;
@ -65,13 +65,13 @@ PciOperateRegister (
OldCommand = Command;
}
return PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
return PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
}
/**
@ -134,33 +134,33 @@ LocateCapabilityRegBlock (
CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1,
&CapabilityPtr
);
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1,
&CapabilityPtr
);
} else {
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
PCI_CAPBILITY_POINTER_OFFSET,
1,
&CapabilityPtr
);
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
PCI_CAPBILITY_POINTER_OFFSET,
1,
&CapabilityPtr
);
}
}
while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
CapabilityPtr,
1,
&CapabilityEntry
);
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
CapabilityPtr,
1,
&CapabilityEntry
);
CapabilityID = (UINT8) CapabilityEntry;

2
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
View File

@ -250,7 +250,7 @@ RegisterPciDevice (
//
PciIo = &(PciIoDevice->PciIo);
Data8 = PCI_INT_LINE_UNKNOWN;
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
//
// Process OpRom

25
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
View File

@ -341,9 +341,8 @@ PciAssignBusNumber (
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIoWrite (
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint16,
Address,
1,
@ -354,9 +353,8 @@ PciAssignBusNumber (
// Initialize SubBusNumber to SecondBus
//
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIoWrite (
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@ -368,9 +366,8 @@ PciAssignBusNumber (
if (IS_PCI_BRIDGE (&Pci)) {
Register8 = 0xFF;
Status = PciRootBridgeIoWrite (
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@ -393,9 +390,8 @@ PciAssignBusNumber (
//
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIoWrite (
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@ -1083,16 +1079,11 @@ ConstructAcpiResourceRequestor (
// If there is at least one type of resource request,
// allocate a acpi resource node
//
Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (Configuration == NULL) {
return EFI_OUT_OF_RESOURCES;
}
ZeroMem (
Configuration,
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
);
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
//
@ -1221,13 +1212,11 @@ ConstructAcpiResourceRequestor (
//
// If there is no resource request
//
Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (Configuration == NULL) {
return EFI_OUT_OF_RESOURCES;
}
ZeroMem (Configuration, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);
Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
@ -1356,7 +1345,7 @@ PciBridgeEnumerator (
SubBusNumber = 0;
StartBusNumber = 0;
PciIo = &(BridgeDev->PciIo);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
if (EFI_ERROR (Status)) {
return Status;

183
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

@ -47,27 +47,25 @@ PciDevicePresent (
//
// Read the Vendor ID register
//
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
NULL,
EfiPciWidthUint32,
Address,
1,
Pci
);
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
1,
Pci
);
if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {
//
// Read the entire config header for the device
//
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
NULL,
EfiPciWidthUint32,
Address,
sizeof (PCI_TYPE00) / sizeof (UINT32),
Pci
);
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
sizeof (PCI_TYPE00) / sizeof (UINT32),
Pci
);
return EFI_SUCCESS;
}
@ -149,7 +147,7 @@ PciPciDeviceInfoCollector (
//
PciIo = &(PciIoDevice->PciIo);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);
if (EFI_ERROR (Status)) {
return Status;
@ -446,10 +444,10 @@ GatherPpbInfo (
//
// Test whether it support 32 decode or not
//
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
if (Value != 0) {
if ((Value & 0x01) != 0) {
@ -629,20 +627,20 @@ BarExisted (
//
// Preserve the original value
//
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
//
// Raise TPL to high level to disable timer interrupt while the BAR is probed
//
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
//
// Write back the original value
//
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
//
// Restore TPL to its original level
@ -860,7 +858,7 @@ GetFastBackToBackSupport (
// Read the status register
//
PciIo = &PciIoDevice->PciIo;
Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
@ -1049,23 +1047,22 @@ DetermineDeviceAttribute (
/**
This routine is used to update the bar information for those incompatible PCI device.
@param PciIoDevice Pci device instance.
@param PciIoDevice Input Pci device instance. Output Pci device instance with updated
Bar information.
@retval EFI_SUCCESS Successfully updated bar information.
@retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
@retval other Failed to check incompatibility device.
**/
EFI_STATUS
UpdatePciInfo (
IN PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
UINTN BarIndex;
UINTN BarEndIndex;
BOOLEAN SetFlag;
EFI_PCI_DEVICE_INFO PciDeviceInfo;
VOID *Configuration;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
@ -1100,22 +1097,6 @@ UpdatePciInfo (
}
if (EFI_ERROR (Status)) {
//
// Check whether the device belongs to incompatible devices from library or not
// If it is , then get its special requirement in the ACPI table
//
if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {
PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;
PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;
PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;
PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;
PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;
Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);
}
}
if (EFI_ERROR (Status) || Configuration == NULL ) {
return EFI_UNSUPPORTED;
}
@ -1193,9 +1174,7 @@ UpdatePciInfo (
Ptr++;
}
if (Configuration != NULL) {
FreePool (Configuration);
}
FreePool (Configuration);
return EFI_SUCCESS;
}
@ -1203,14 +1182,14 @@ UpdatePciInfo (
/**
This routine will update the alignment with the new alignment.
@param Alignment Old alignment.
@param Alignment Input Old alignment. Output updated alignment.
@param NewAlignment New alignment.
**/
VOID
SetNewAlign (
IN UINT64 *Alignment,
IN UINT64 NewAlignment
IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment
)
{
UINT64 OldAlignment;
@ -1298,11 +1277,11 @@ PciParseBar (
Value = 0;
Status = BarExisted (
PciIoDevice,
Offset,
&Value,
&OriginalValue
);
PciIoDevice,
Offset,
&Value,
&OriginalValue
);
if (EFI_ERROR (Status)) {
PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
@ -1400,11 +1379,11 @@ PciParseBar (
Offset += 4;
Status = BarExisted (
PciIoDevice,
Offset,
&Value,
&OriginalValue
);
PciIoDevice,
Offset,
&Value,
&OriginalValue
);
if (EFI_ERROR (Status)) {
return Offset + 4;
@ -1482,7 +1461,7 @@ InitializePciDevice (
// has not been alloacted
//
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
}
}
@ -1506,28 +1485,28 @@ InitializePpb (
// Io32, pMem32, pMem64 to quiescent state
// Resource base all ones, Resource limit all zeros
//
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
//
// don't support use io32 as for now
// Don't support use io32 as for now
//
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
//
// Force Interrupt line to zero for cards that come up randomly
//
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
}
/**
@ -1550,22 +1529,22 @@ InitializeP2C (
// Io32, pMem32, pMem64 to quiescent state(
// Resource base all ones, Resource limit all zeros
//
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
//
// Force Interrupt line to zero for cards that come up randomly
//
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
}
/**
@ -1722,9 +1701,9 @@ PciEnumeratorLight (
RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
Status = PciPciDeviceInfoCollector (
RootBridgeDev,
(UINT8) MinBus
);
RootBridgeDev,
(UINT8) MinBus
);
if (!EFI_ERROR (Status)) {
@ -1995,25 +1974,24 @@ ResetAllPpbBusNumber (
// Check to see whether a pci device is present
//
Status = PciDevicePresent (
PciRootBridgeIo,
&Pci,
StartBusNumber,
Device,
Func
);
PciRootBridgeIo,
&Pci,
StartBusNumber,
Device,
Func
);
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {
Register = 0;
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint32,
Address,
1,
&Register
);
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
1,
&Register
);
SecondaryBus = (UINT8)(Register >> 8);
if (SecondaryBus != 0) {
@ -2024,9 +2002,8 @@ ResetAllPpbBusNumber (
// Reset register 18h, 19h, 1Ah on PCI Bridge
//
Register &= 0xFF000000;
Status = PciRootBridgeIoWrite (
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint32,
Address,
1,

12
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
View File

@ -246,29 +246,29 @@ DetermineDeviceAttribute (
/**
This routine is used to update the bar information for those incompatible PCI device.
@param PciIoDevice Pci device instance.
@param PciIoDevice Input Pci device instance. Output Pci device instance with updated
Bar information.
@retval EFI_SUCCESS Successfully updated bar information.
@retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
@retval other Failed to check incompatibility device.
**/
EFI_STATUS
UpdatePciInfo (
IN PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
This routine will update the alignment with the new alignment.
@param Alignment Old alignment.
@param Alignment Input Old alignment. Output updated alignment.
@param NewAlignment New alignment.
**/
VOID
SetNewAlign (
IN UINT64 *Alignment,
IN UINT64 NewAlignment
IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment
);
/**

19
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
View File

@ -628,12 +628,12 @@ PciIoConfigRead (
}
Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
PciIoDevice->PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Address,
Count,
Buffer
);
PciIoDevice->PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Address,
Count,
Buffer
);
if (EFI_ERROR (Status)) {
ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
@ -1628,16 +1628,11 @@ PciIoGetBarAttributes (
NumConfig = 1;
}
Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (Configuration == NULL) {
return EFI_OUT_OF_RESOURCES;
}
ZeroMem (
Configuration,
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
);
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
if (NumConfig == 1) {

956
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

File diff suppressed because it is too large Load Diff

116
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h
View File

@ -15,14 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#ifndef _EFI_PCI_LIB_H_
#define _EFI_PCI_LIB_H_
//
// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
//
#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01
#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02
#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04
#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08
#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x10
typedef struct {
EFI_HANDLE Handle;
@ -146,113 +138,7 @@ PciHostBridgeP2CProcess (
**/
EFI_STATUS
PciHostBridgeEnumerator (
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoRead (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
If PCI incompatibility check is enabled, do incompatibility check.
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of PCI configuration operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoWrite (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci, OPTIONAL
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
#endif

50
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
View File

@ -216,9 +216,10 @@ LoadFile2 (
}
/**
Get Pci device's oprom infor bits.
Get Pci device's oprom information.
@param PciIoDevice Pci device instance.
@param PciIoDevice Input Pci device instance.
Output Pci device instance with updated OptionRom size.
@retval EFI_NOT_FOUND Pci device has not Option Rom.
@retval EFI_SUCCESS Pci device has Option Rom.
@ -226,7 +227,7 @@ LoadFile2 (
**/
EFI_STATUS
GetOpRomInfo (
IN PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
UINT8 RomBarIndex;
@ -255,11 +256,7 @@ GetOpRomInfo (
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
//
// If is ppb
//
//
// 0x38
// If is ppb, 0x38
//
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
@ -269,9 +266,8 @@ GetOpRomInfo (
AllOnes = 0xfffffffe;
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
Status = PciRootBridgeIoWrite (
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32,
Address,
1,
@ -284,9 +280,8 @@ GetOpRomInfo (
//
// Read back
//
Status = PciRootBridgeIoRead (
Status = PciRootBridgeIo->Pci.Read(
PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32,
Address,
1,
@ -295,6 +290,7 @@ GetOpRomInfo (
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
//
// Bits [1, 10] are reserved
//
@ -558,7 +554,7 @@ RomDecode (
// Clear all bars
//
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
}
//
@ -566,13 +562,13 @@ RomDecode (
// enable its decoder
//
Value32 = RomBar | 0x1;
PciIoWrite (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
);
PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
);
//
// Programe all upstream bridge
@ -600,13 +596,13 @@ RomDecode (
// disable rom decode
//
Value32 = 0xFFFFFFFE;
PciIoWrite (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
);
PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
);
}
}

7
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h
View File

@ -78,9 +78,10 @@ ContainEfiImage (
/**
Get Pci device's oprom infor bits.
Get Pci device's oprom information.
@param PciIoDevice Pci device instance.
@param PciIoDevice Input Pci device instance.
Output Pci device instance with updated OptionRom size.
@retval EFI_NOT_FOUND Pci device has not Option Rom.
@retval EFI_SUCCESS Pci device has Option Rom.
@ -88,7 +89,7 @@ ContainEfiImage (
**/
EFI_STATUS
GetOpRomInfo (
IN PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**

14
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c
View File

@ -55,13 +55,13 @@ ResetPowerManagementFeature (
//
// Write PMCSR
//
PciIoWrite (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
PowerManagementRegBlock + 4,
1,
&PowerManagementCSR
);
PciIoDevice->PciIo.Pci.Write (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
PowerManagementRegBlock + 4,
1,
&PowerManagementCSR
);
return EFI_SUCCESS;
}

481
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
View File

@ -91,8 +91,8 @@ SkipIsaAliasAperture (
**/
VOID
InsertResourceNode (
IN PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
)
{
LIST_ENTRY *CurrentLink;
@ -352,7 +352,6 @@ CalculateResourceAperture (
//
// Apply padding resource if available
//
Offset = Aperture & (Node->Alignment);
if (Offset != 0) {
@ -375,7 +374,6 @@ CalculateResourceAperture (
//
// Consider the aperture alignment
//
CurrentLink = CurrentLink->ForwardLink;
}
@ -423,12 +421,12 @@ CalculateResourceAperture (
**/
VOID
GetResourceFromDevice (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
)
{
@ -582,14 +580,12 @@ CreateResourceNode (
Node = NULL;
Node = AllocatePool (sizeof (PCI_RESOURCE_NODE));
Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));
ASSERT (Node != NULL);
if (Node == NULL) {
return NULL;
}
ZeroMem (Node, sizeof (PCI_RESOURCE_NODE));
Node->Signature = PCI_RESOURCE_SIGNATURE;
Node->PciDev = PciDev;
Node->Length = Length;
@ -617,12 +613,12 @@ CreateResourceNode (
**/
VOID
CreateResourceMap (
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *Bridge,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
)
{
PCI_IO_DEVICE *Temp;
@ -726,7 +722,7 @@ CreateResourceMap (
IoBridge
);
} else {
gBS->FreePool (IoBridge);
FreePool (IoBridge);
IoBridge = NULL;
}
@ -742,7 +738,7 @@ CreateResourceMap (
Mem32Bridge
);
} else {
gBS->FreePool (Mem32Bridge);
FreePool (Mem32Bridge);
Mem32Bridge = NULL;
}
@ -758,7 +754,7 @@ CreateResourceMap (
PMem32Bridge
);
} else {
gBS->FreePool (PMem32Bridge);
FreePool (PMem32Bridge);
PMem32Bridge = NULL;
}
@ -774,7 +770,7 @@ CreateResourceMap (
Mem64Bridge
);
} else {
gBS->FreePool (Mem64Bridge);
FreePool (Mem64Bridge);
Mem64Bridge = NULL;
}
@ -790,7 +786,7 @@ CreateResourceMap (
PMem64Bridge
);
} else {
gBS->FreePool (PMem64Bridge);
FreePool (PMem64Bridge);
PMem64Bridge = NULL;
}
@ -799,7 +795,6 @@ CreateResourceMap (
//
// If it is P2C, apply hard coded resource padding
//
//
if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {
ResourcePaddingForCardBusBridge (
Temp,
@ -813,7 +808,7 @@ CreateResourceMap (
CurrentLink = CurrentLink->ForwardLink;
}
//
//
// To do some platform specific resource padding ...
//
@ -1120,13 +1115,13 @@ ProgramBar (
case PciBarTypeMem32:
case PciBarTypePMem32:
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
@ -1137,23 +1132,23 @@ ProgramBar (
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address32
);
Address32 = (UINT32) RShiftU64 (Address, 32);
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
1,
&Address32
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
@ -1205,13 +1200,13 @@ ProgramPpbApperture (
case PPB_BAR_0:
case PPB_BAR_1:
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
@ -1221,41 +1216,41 @@ ProgramPpbApperture (
case PPB_IO_RANGE:
Address32 = ((UINT32) (Address)) >> 8;
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x1C,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint8,
0x1C,
1,
&Address32
);
Address32 >>= 8;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x30,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
0x30,
1,
&Address32
);
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 8;
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x1D,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint8,
0x1D,
1,
&Address32
);
Address32 >>= 8;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x32,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
0x32,
1,
&Address32
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
@ -1264,23 +1259,23 @@ ProgramPpbApperture (
case PPB_MEM32_RANGE:
Address32 = ((UINT32) (Address)) >> 16;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x20,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
0x20,
1,
&Address32
);
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x22,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
0x22,
1,
&Address32
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
@ -1290,41 +1285,41 @@ ProgramPpbApperture (
case PPB_PMEM64_RANGE:
Address32 = ((UINT32) (Address)) >> 16;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x24,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
0x24,
1,
&Address32
);
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x26,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
0x26,
1,
&Address32
);
Address32 = (UINT32) RShiftU64 (Address, 32);
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x28,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
0x28,
1,
&Address32
);
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x2C,
1,
&Address32
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
0x2C,
1,
&Address32
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
@ -1707,77 +1702,77 @@ ProgramP2C (
switch (Node->Bar) {
case P2C_BAR_0:
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
1,
&Address
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
break;
case P2C_MEM_1:
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_0,
1,
&Address
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_0,
1,
&Address
);
TempAddress = Address + Node->Length - 1;
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_LIMIT_0,
1,
&TempAddress
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_LIMIT_0,
1,
&TempAddress
);
if (Node->ResType == PciBarTypeMem32) {
//
// Set non-prefetchable bit
//
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
} else {
//
// Set pre-fetchable bit
//
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
}
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
@ -1787,67 +1782,67 @@ ProgramP2C (
break;
case P2C_MEM_2:
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_1,
1,
&Address
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_BASE_1,
1,
&Address
);
TempAddress = Address + Node->Length - 1;
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_LIMIT_1,
1,
&TempAddress
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_MEMORY_LIMIT_1,
1,
&TempAddress
);
if (Node->ResType == PciBarTypeMem32) {
//
// Set non-prefetchable bit
//
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
} else {
//
// Set pre-fetchable bit
//
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint16,
PCI_CARD_BRIDGE_CONTROL,
1,
&BridgeControl
);
}
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
@ -1856,22 +1851,22 @@ ProgramP2C (
break;
case P2C_IO_1:
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_0_LOWER,
1,
&Address
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_0_LOWER,
1,
&Address
);
TempAddress = Address + Node->Length - 1;
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_LIMIT_0_LOWER,
1,
&TempAddress
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_LIMIT_0_LOWER,
1,
&TempAddress
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
@ -1880,22 +1875,22 @@ ProgramP2C (
break;
case P2C_IO_2:
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_1_LOWER,
1,
&Address
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_BASE_1_LOWER,
1,
&Address
);
TempAddress = Address + Node->Length - 1;
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_LIMIT_1_LOWER,
1,
&TempAddress
);
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
PCI_CARD_IO_LIMIT_1_LOWER,
1,
&TempAddress
);
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;

28
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h
View File

@ -76,8 +76,8 @@ SkipIsaAliasAperture (
**/
VOID
InsertResourceNode (
IN PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
);
/**
@ -142,12 +142,12 @@ CalculateResourceAperture (
**/
VOID
GetResourceFromDevice (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**
@ -188,12 +188,12 @@ CreateResourceNode (
**/
VOID
CreateResourceMap (
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *Bridge,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**